Flexible and reconfigurable mismatch-tolerant serial clock distribution networks
A Chattopadhyay, Z Zilic - … on very large scale integration (VLSI …, 2011 - ieeexplore.ieee.org
We present a clock distribution network that emphasizes flexibility and layout independence.
It suits a variety of applications, clock domain shapes and sizes using a modular, standard …
It suits a variety of applications, clock domain shapes and sizes using a modular, standard …
Wave propagation on networks of probabilistic inverter cells
N Hirami, T Kamio, H Fujisaka - Nonlinear Theory and Its …, 2024 - jstage.jst.go.jp
Three types of networks, neighbor-coupled, all-coupled, and cross-coupled networks, are
analyzed numerically or analytically. Inverter cells organizing these networks are built of …
analyzed numerically or analytically. Inverter cells organizing these networks are built of …
Techniques for low jitter clock multiplication
BM Helal - 2008 - dspace.mit.edu
Phase realigning clock multipliers, such as Multiplying Delay-Locked Loops (MDLL), offer
significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is …
significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is …
Dual reference signal post-silicon reconfigurable clock distribution networks
A Chattopadhyay - 2009 - escholarship.mcgill.ca
This thesis investigates the use of averaging techniques in the development of clock
distribution networks and an on-chip clock skew measurement circuit. Our flexible clock …
distribution networks and an on-chip clock skew measurement circuit. Our flexible clock …