Dynamically managing the communication-parallelism trade-off in future clustered processors

R Balasubramonian, S Dwarkadas… - Proceedings of the 30th …, 2003 - dl.acm.org
Clustered microarchitectures are an attractive alternative to large monolithic superscalar
designs due to their potential for higher clock rates in the face of increasingly wire-delay …

Consequence-based Clustered Architecture

S Karunakar, R Kalayappan, S Chandran - ACM Transactions on …, 2024 - dl.acm.org
We recognize that the execution of many dynamic instructions have no consequence on the
overall execution of the program. For example, the execution of a correctly predicted …

An empirical study of the scalability aspects of instruction distribution algorithms for clustered processors

A Aggarwal, M Franklin - … on Performance Analysis of Systems and …, 2001 - computer.org
Tsunami is a series of water waves caused by submarine earthquakes leading to the
displacement of a large volume of water. The earliest known tsunami was recorded in 1450 …

Improving diagnosis resolution of a fault detection test set

A Riefert, M Sauer, S Reddy… - 2015 IEEE 33rd VLSI …, 2015 - ieeexplore.ieee.org
Manufactured VLSI circuits using a new technology typically suffer from systematic defects
that are process-dependent and at sub-nanometer feature sizes such defects may be even …

Instruction replication for reducing delays due to inter-PE communication latency

A Aggarwal, M Franklin - IEEE Transactions on Computers, 2005 - ieeexplore.ieee.org
As feature sizes are becoming smaller, wire delays are becoming very critical. Clustering is
a popular decentralization approach to reduce the impact of shrinking technologies on clock …

Hierarchical interconnects for on-chip clustering

A Aggarwal, M Franklin - Proceedings 16th International …, 2002 - ieeexplore.ieee.org
In the sub-micron technology era, wire delays are becoming much more important than gate
delays, making it particularly attractive to go for clustered designs. A common form of …

[PDF][PDF] Exploring the design space for 3D clustered architectures

M Awasthi, R Balasubramonian - Proceedings of the 3rd IBM Watson …, 2006 - Citeseer
Abstract 3D die-stacked chips are emerging as intriguing prospects for the future because of
their ability to reduce on-chip wire delays and power consumption. However, they will likely …

Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration

R Balasubramonian, S Dwarkadas… - US Patent …, 2012 - Google Patents
In a processor having multiple clusters which operate in par allel, the number of clusters in
use can be varied dynamically. At the start of each program phase, the configuration option …

Power efficient resource scaling in partitioned architectures through dynamic heterogeneity

N Muralimanohar, K Ramani… - … Analysis of Systems …, 2006 - ieeexplore.ieee.org
The ever increasing demand for high clock speeds and the desire to exploit abundant
transistor budgets have resulted in alarming increases in processor power dissipation …

Dynamic Ineffectuality-based Clustered Architectures

R Kalayappan, S Chandran - arXiv preprint arXiv:2304.12762, 2023 - arxiv.org
The direction of conditional branches is predicted correctly in modern processors with great
accuracy. We find several instructions in the dynamic instruction stream that contribute only …