This paper introduces a quadrature fractional-N cascaded frequency synthesizer and its
phase noise analysis, optimization, and design for future 5G wireless transceivers. The …

We introduce a single-loop PLL that operates in a narrower-bandwidth, integer-N mode
during phase lock and in a wider-bandwidth, fractional-N mode during transient. This hybrid …

An LC-VCO based phase-locked loop (PLL) frequency synthesizer which incorporates loop
bandwidth tracking is described. In order to minimize loop bandwidth variations resulting …

The implementation of wideband mm-wave radars for automotive applications necessitates
wideband, fast, and precise linear frequency modulation generation. In this paper, we …

A 1.5-V 256-263 8-modulus prescaler and a 1.5-V integer-N phase-locked loop (PLL) with
eight different output frequencies have been implemented in a 0.13-mum foundry CMOS …

A 1-V 24-GHz 17.5-mW fully integrated phase-locked loop employing a transformer-
feedback voltage-controlled oscillator and a stacked divide-by-2 frequency divider for low …

A wide range differentially tuned LC PLL using dual switched capacitor VCOs was designed
in a 65 nm standard CMOS process for a forwarded clock link. Bandwidth and stability were …

In this thesis the theory and implementation of a digital bang-bang frequency synthesizer for
application in the field of high speed serial data communications systems is presented. The …

The paper studies low-power ultra wideband (UWB) transceiver architectures. First, three
different architectures for the impulse-radio UWB transceiver are studied, while investigating …

This letter presents the design and fabrication of a Ku-band differential-mode voltage-
controlled oscillator (VCO) with extremely low power consumption and good phase noise …