New structure transistors for advanced technology node CMOS ICs

Q Zhang, Y Zhang, Y Luo, H Yin - National Science Review, 2024 - academic.oup.com
Over recent decades, advancements in complementary metal-oxide-semiconductor
integrated circuits (ICs) have mainly relied on structural innovations in transistors. From …

Low-temperature atomic-level trimming on Ge interfused surface for gate-all-around Si nanosheets transistors

GQ Sang, RJ Jiang, YZ Wei, QK Li, MH Zhang, JX Yao… - Rare Metals, 2024 - Springer
In order to effectively remove the residual Ge atoms at the surface of channel and improve
the interfacial characteristic of gate-all-around (GAA) Si nanosheet field effect transistors, a …

Investigation of fabricated CMOS fishboneFETs and treeFETs with strained SiGe nano-fins on bulk-Si substrate

L Cao, Q Zhang, J Yao, J Li, Y Liu, Y Luo… - IEEE Electron …, 2023 - ieeexplore.ieee.org
Based on the bulk-Si substrate, the CMOS tree-like FETs including the FishboneFETs with
bottom SiGe nano-fin and the TreeFETs without bottom SiGe nano-fin were both designed …

Electrical characteristics of Si0. 7Ge0. 3/Si heterostructure-based n-type GAA MOSFETs

P Raj, KS Chang-Liao, PK Tiwari - Microelectronic Engineering, 2024 - Elsevier
Abstract Electrical characteristics of Si 0.7 Ge 0.3/Si heterostructure-based n-type gate-all-
around MOSFETs (GAA MOSFETs) are reported in this work through experimental and …

Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process

X Zhu, L Cao, G Wang, H Yin - Nanomaterials, 2024 - mdpi.com
Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have
demonstrated promising quantum properties and the potential application of advanced Si …

Improved breakdown performance in recessed-gate normally off GaN MIS-HEMTs by regrown fishbone trench

JQ He, PR Wang, FZ Du, KY Wen, Y Jiang… - Applied Physics …, 2024 - pubs.aip.org
This work develops a regrown fishbone trench (RFT) structure in selective area growth
(SAG) technique to fabricate recessed-gate normally off GaN metal–insulator …

Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond

X Zhang, J Yao, Y Luo, L Cao, Y Zheng… - … on Electron Devices, 2024 - ieeexplore.ieee.org
The implementation of vertically stacked gate-all-around nanosheet FET (GAA NSFET) may
help improve the performance of static random access memory (SRAM) for the design …

Impact of ambient temperature on CombFET for sub-5-nm technology nodes: An RF performance perspective

P Srinivas, NA Kumari, A Kumar, PK Tiwari… - Microsystem …, 2024 - Springer
This paper explores the impact of ambient temperature on the RF performance parameters
of CombFET device. The CombFET has been considered one of the most realistic …

Investigation of Electro-Thermal Performance for TreeFET from the Perspective of Structure Parameters

W Liu, X Pan, J Liu, Q Li - Electronics, 2023 - mdpi.com
In this work, the electro-thermal properties of TreeFET, which combines vertically stacked
nanosheet (NS) and fin-shaped interbridge (IB) channels, are investigated in terms of …

7 Scope and challenges

A Rahimifar, Z Ramezani - Device Circuit Co-Design Issues in …, 2023 - books.google.com
Various solutions have been proposed in recent years to address the problem of short-
channel effects (SCEs) in the field effect transistors (FETs) during downscaling [1–4]. The …