Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof

SJ Kweskin - US Patent 11,114,332, 2021 - Google Patents
US11114332B2 - Semiconductor on insulator structure comprising a plasma nitride layer and
method of manufacture thereof - Google Patents US11114332B2 - Semiconductor on insulator …

Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers

I Peidous, JL Libbert, S Kommu, AM Jones… - US Patent …, 2019 - Google Patents
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a
semiconductor-on-insulator device is provided. The single crystal semiconductor handle …

Integrated passive device on soi substrate

DS Whitefield, JF Mason - US Patent App. 15/219,596, 2017 - Google Patents
Filed: Jul. 26, 2016(57) A method for fabricating dual-tier radio-frequency devices Related
US Application Data involves providing a silicon-on-insulator integrated circuit (60) …

Process flow for manufacturing semiconductor on insulator structures in parallel

I Peidous, AM Jones, S Kommu, JL Libbert - US Patent 9,831,115, 2017 - Google Patents
US9831115B2 - Process flow for manufacturing semiconductor on insulator structures in
parallel - Google Patents US9831115B2 - Process flow for manufacturing semiconductor on …

Method and apparatus for high performance passive-active circuit integration

JF Mason, DS Whitefield, DC Bartle… - US Patent App. 15 …, 2016 - Google Patents
US20160379943A1 - Method and apparatus for high performance passive-active circuit
integration - Google Patents US20160379943A1 - Method and apparatus for high …

High resistivity SOI wafers and a method of manufacturing thereof

I Peidous, S Kommu, G Wang, SG Thomas - US Patent 10,079,170, 2018 - Google Patents
A high resistivity single crystal semiconductor handle structure for use in the manufacture of
SOI structure is provided. The handle structure comprises an intermediate semiconductor …

High resistivity silicon-on-insulator structure and method of manufacture thereof

JL Libbert, Q Liu, G Wang, AM Jones - US Patent 10,468,295, 2019 - Google Patents
US10468295B2 - High resistivity silicon-on-insulator structure and method of manufacture thereof
- Google Patents US10468295B2 - High resistivity silicon-on-insulator structure and method of …

Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress

G Wang, JL Libbert, SG Thomas, I Peidous - US Patent 10,283,402, 2019 - Google Patents
A semiconductor on insulator multilayer structure is provided. The multilayer comprises a
high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or …

High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency

G Wang, JL Libbert, SG Thomas, Q Liu - US Patent 10,546,771, 2020 - Google Patents
(57) ABSTRACT A multilayer semiconductor on insulator structure is pro vided in which the
handle substrate and an epitaxial layer in interfacial contact with the handle substrate …

High resistivity silicon-on-insulator substrate comprising an isolation region

I Peidous, JL Libbert - US Patent 10,269,617, 2019 - Google Patents
2013/0120951 A1 5/2013 Zuo et al. 2013/0122672 AL 5/2013 Or-Bach et al. 2013/0168835
A1 7/2013 Botula et al. 2013/0193445 A1 8/2013 Dennard et al. 2013/0294038 Al 11/2013 …