In this work, a comparison has been made between a low noise ring-oscillator and an LC-
oscillator Phase Locked Loop (PLL). An ASIC has been developed to conduct irradiation …

This paper presents a radiation tolerant phase-locked loop CMOS application-specified
integrated circuit with an optimized voltage controlled oscillator (VCO) for single-event …

This article presents a radiation tolerant charge-pump phase-locked loop (PLL) with low
static phase error variability suitable for high-performance clock systems in high-dose …

A 30-MHz voltage-mode buck converter using a delay-line-based pulse-width-modulation
controller is proposed in this brief. Two voltage-to-delay cells are used to convert the voltage …

This brief presents a 7-b 32-GS/s successive approximation register analog-to-digital
converter (ADC) using a massive time-interleaving (TI) architecture. For low-skew multi …

This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with a
resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor …

For this task, an improved phase locked loop (PLL) was developed using a more
sophisticated phase‐frequency detector with multiband flexible dividers that provide …

This article proposes a radiation-tolerant phase-locked loop (PLL) for space-based
applications. The proportional and integral path is proposed to mitigate the single-event …

A novel radiation hardened by design LVDS/SLVS receiver is designed and simulated in 65
nm CMOS technology. The receiver is capable of receiving a 2.56 Gbps signal with less than …

In this paper, an ultra low power, fully synthesizable digital phase and frequency detector
(DPFD) is presented for all digital phase lock loop (ADPLL) applications in bluetooth low …