We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a
single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The …

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm
CMOS process. The transceiver is architectured from the ground up to be compatible with …

A new and innovative paradigm for RF frequency synthesis and wireless transmitter design
Learn the techniques for designing and implementing an all-digital RF frequency …

An all-digital PLL for wireline applications is designed with a sub-exponent TDC which
adaptively scales its resolution according to input time difference. By cascading 2× time …

A fully digital frequency synthesizer for RF wireless applications has recently been
proposed. At its foundation lies a digitally controlled oscillator that deliberately avoids any …

In this brief, a systematic design procedure for a second-order all-digital phase-locked loop
(PLL) is proposed. The design procedure is based on the analogy between a type-II second …

(57) ABSTRACT A novel apparatus and method of linearization of a digitally controlled pre-
power amplifier (DPA) and RF power ampli fier (PA). The mechanism is operative to perform …

An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully
programmable proportional-integral-differential (PID) loop filter and features a third order …

We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular
mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver …

The use of bang-bang phase-locked loops (BBPLLs) has become increasingly common in a
lot of communications systems, in particular in the area of clock and data recovery. Although …