A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate

D Nayak, DP Acharya, PK Rout, U Nanda - Microelectronics Journal, 2018 - Elsevier
The impact of alpha particle and exposure to cosmic radiation has multifold the existing
stability issue associated with modern sub-100 nm SRAM cell design. Noise insertion in the …

Design and Analysis of Ultra High Speed 16 Channel Cascaded EDF A-DWDM Network with Post Dispersion Compensations Using Optimization of Fiber Bragg …

M Singh, D Kumar, D Somwanshi - 2020 5th IEEE International …, 2020 - ieeexplore.ieee.org
This article introduces an optimization of optical network system using the residual power of
doped-fiber amplifier (EDFA) and optimized dispersion management by fiber bragg grating …

Design of novel SRAM cell using hybrid VLSI techniques for low leakage and high speed in embedded memories

K Gavaskar, US Ragupathy, V Malini - Wireless Personal Communications, 2019 - Springer
Static or leakage power is the dominating component of total power dissipation in deep
nanometer technologies below 90 nm, which has resulted in increase from 18% at 130 nm …

Nanoscale CMOS static random access memory (SRAM) design: Trends and challenges

S Ambulkar, JK Mishra - Advanced MOS Devices and their Circuit …, 2024 - taylorfrancis.com
The enormous demand for electronic devices has sparked a new revolution in VLSI
technology. VLSI technology applications have extensively expanded to various electronic …

Design and comparative analysis of SRAM array using low leakage controlled transistor technique with improved delay

K Gavaskar, MS Narayanan, MS Nachammal… - Journal of Ambient …, 2022 - Springer
Static random access memory power and speed dissipation are the significant factor in most
of the electronic applications, which prompts numerous plans with the power utilization of …

A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor

D Nayak, DP Acharya, K Mahapatra - AEU-International Journal of …, 2017 - Elsevier
Energy consumption and data stability are vital requirement of cache in embedded
processor. SRAM is a natural choice for cache memory owing to their speed and energy …

A novel approach to design SRAM cells for low leakage and improved stability

T Tripathi, DS Chauhan, SK Singh - Journal of Low Power Electronics and …, 2018 - mdpi.com
The semiconductor electronic industry is advancing at a very fast pace. The size of portable
and handheld devices are shrinking day by day and the demand for longer battery backup is …

A novel charge recycle read write assist technique for energy efficient and fast 20 nm 8T-SRAM array

D Nayak, DP Acharya, PK Rout, U Nanda - Solid-State Electronics, 2018 - Elsevier
The read instability of conventional 6T-SRAM cell has made the 8T-SRAM cell a substitute
for high data reliability. But the single ended nature of read operation demands a complete V …

Design and implementation of different types of full adders in ALU and leakage minimization

SK Pattnaik, U Nanda, D Nayak… - … on Trends in …, 2017 - ieeexplore.ieee.org
In the era of nanotechnology, leakage current, active power, delay, area bear an important
metric for design and analysis of complex arithmetic logic circuits. In this paper major work …

Proposed design of 1 KB memory array structure for cache memories

K Gavaskar, US Ragupathy, V Malini - Wireless Personal Communications, 2019 - Springer
Technology scaling facilitates to meet ever increasing demands for a portable and battery
operated systems, at the same time causes diminution of length of the channel, gate oxide …