Machine learning for electronic design automation: A survey

G Huang, J Hu, Y He, J Liu, M Ma, Z Shen… - ACM Transactions on …, 2021 - dl.acm.org
With the down-scaling of CMOS technology, the design complexity of very large-scale
integrated is increasing. Although the application of machine learning (ML) techniques in …

MLCAD: A survey of research in machine learning for CAD keynote paper

M Rapp, H Amrouch, Y Lin, B Yu… - … on Computer-Aided …, 2021 - ieeexplore.ieee.org
Due to the increasing size of integrated circuits (ICs), their design and optimization phases
(ie, computer-aided design, CAD) grow increasingly complex. At design time, a large design …

A survey of machine learning for computer architecture and systems

N Wu, Y Xie - ACM Computing Surveys (CSUR), 2022 - dl.acm.org
It has been a long time that computer architecture and systems are optimized for efficient
execution of machine learning (ML) models. Now, it is time to reconsider the relationship …

Versatile multi-stage graph neural network for circuit representation

S Yang, Z Yang, D Li, Y Zhang… - Advances in …, 2022 - proceedings.neurips.cc
Due to the rapid growth in the scale of circuits and the desire for knowledge transfer from old
designs to new ones, deep learning technologies have been widely exploited in Electronic …

DE-HNN: An effective neural model for Circuit Netlist representation

Z Luo, TS Hy, P Tabaghi, M Defferrard… - International …, 2024 - proceedings.mlr.press
The run-time for optimization tools used in chip design has grown with the complexity of
designs to the point where it can take several days to go through one design cycle which …

Circuitnet: An open-source dataset for machine learning in vlsi cad applications with improved domain-specific evaluation metric and learning strategies

Z Chai, Y Zhao, W Liu, Y Lin, R Wang… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The design automation community has been actively exploring machine learning (ML) for
very-large-scale-integrated (VLSI) computer-aided design (CAD). Many studies have …

LHNN: Lattice hypergraph neural network for VLSI congestion prediction

B Wang, G Shen, D Li, J Hao, W Liu, Y Huang… - Proceedings of the 59th …, 2022 - dl.acm.org
Precise congestion prediction from a placement solution plays a crucial role in circuit
placement. This work proposes the lattice hypergraph (LH-graph), a novel graph formulation …

Global placement with deep learning-enabled explicit routability optimization

S Liu, Q Sun, P Liao, Y Lin, B Yu - 2021 Design, Automation & …, 2021 - ieeexplore.ieee.org
Placement and routing (PnR) is the most time-consuming part of the physical design flow.
Recognizing the routing performance ahead of time can assist designers and design tools to …

Robust GNN-based representation learning for HLS

A Sohrabizadeh, Y Bai, Y Sun… - 2023 IEEE/ACM …, 2023 - ieeexplore.ieee.org
The efficient and timely optimization of microarchitecture for a target application is hindered
by the long evaluation runtime of a design candidate, creating a serious burden. To tackle …

Circuit as set of points

J Zou, X Wang, J Guo, W Liu… - Advances in Neural …, 2024 - proceedings.neurips.cc
As the size of circuit designs continues to grow rapidly, artificial intelligence technologies are
being extensively used in Electronic Design Automation (EDA) to assist with circuit design …