With the rapid advancement of CMOS technologies, nano-scale CMOS latches have
become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations …

SRAM SER measurements across technology nodes indicate that while scaling from planar
to the first FinFET process provided a large reduction in per-bit SER, the subsequent scaling …

SRAM SER measurements across technology nodes indicate that while scaling from planar
processes down to the 7-nm FinFET process provided a reduction in the per-bit SER at …

Tunnel field-effect transistors (TFETs) have promising structures for future ultrascaled
devices thanks to their capability in reducing swing threshold and short channel effects. In …

Using error-correcting codes (ECCs) is considered one of the most effective ways to mask
the effects of radiation-induced faults in memory and computing devices. Unfortunately, with …

For advanced technology nodes, the close proximity of semiconductor regions results in
multiple regions collecting charge after an ion strike. This is especially true for static random …

The dependence of single-event transients on strike location is studied and integrated into
the bias-dependent single-event model for circuit simulation. Two nondimensional …

Scaling trends in the alpha-particle and neutron induced SRAM SER shows an increase in
the per-bit SER and percent multi-cell upsets at the 5-nm FinFET process compared to the 7 …

Soft error rates (SER) are characterized for the 5-nm bulk FinFET D flip-flops for alpha
particles, thermal neutrons, and high-energy neutrons as a function of supply voltage. At …

In this work, single-event upset (SEU) responses of D flip-flop (FF) designs with different
threshold-voltage options in a 7-nm bulk FinFET technology are examined. Experimental …