Ever shrinking technologies in VLSI era made it possible to place several IP (Intellectual
Property) blocks onto a single die. This technology improvement also brought the challenge …

Ever shrinking technologies in VLSI era made it possible to place several modules onto a
single die. However, the need for the new communication methods has also increased …

Network-on-Chip (NoC) is a newly introduced paradigm to overcome the communication
problems of System-on-Chip architectures. Mapping applications onto mesh-based NoC …

Due to shrinking technology sizes, more and more processing elements and memory blocks
are being integrated on a single die. However, traditional communication infrastructures (eg …

As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor
densities on chips dramatically increase. While nanometer feature sizes allow denser chip …

This paper extends the basic Kernighan–Lin graph bi-partitioning algorithm for partitioning
core graphs of applications to be designed using Network-on-Chip (NoC) concept. Mapping …

Network-on-chip (NoC) is an alternative approach to traditional communication methods for
system-on-chip architectures. Irregular topologies are preferable for the application specific …

Network on Chip (NoC) is a new communication medium used for systems-on-chip (SoCs).
In an SoC, the placement of the communicating elements across the network has an impact …

A genetic algorithm based mapping and routing approach called GAMR is proposed for low
energy design of 2D mesh based Network on chip (NoC) under communication bandwidth …

This paper analyzes the main sources of power consumption in Networks-on-Chip (NoC)-
based systems. Analytical power models of global interconnection links are studied at …