Hardware and software enabled implementation of power profile management instructions in system on chip
R Kaushal, A Gangwar, VM Pusuluri… - US Patent 9,568,970, 2017 - Google Patents
Aspects of the present disclosure relate to a method and system for hybrid and/or distributed
implementation of generation and/or execution of power profile management instructions …
implementation of generation and/or execution of power profile management instructions …
Configurable router for a network on chip (NoC)
J Philip, S Kumar - US Patent 9,742,630, 2017 - Google Patents
Example implementations described herein are directed to a configurable building block,
such as a router, for implementation of a Network on Chip (NoC). The router is …
such as a router, for implementation of a Network on Chip (NoC). The router is …
Systems and methods for facilitating low power on a network-on-chip
JA Bauman, J Rowlands, S Kumar - US Patent 10,452,124, 2019 - Google Patents
Aspects of the present disclosure are directed to a power specification and Network on Chip
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …
System and method for visualization of NoC performance based on simulation output
Aspects of the present disclosure are directed to methods, systems, and non-transitory
computer readable mediums for selective visualization and performance characterization of …
computer readable mediums for selective visualization and performance characterization of …
Supporting multicast in NoC interconnect
Example implementations are directed to more efficiently delivering a multicast message to
multiple destination components from a source component. Multicast environment is …
multiple destination components from a source component. Multicast environment is …
System level simulation in Network on Chip architecture
S Kumar, A Patankar, E Norige - US Patent 10,496,770, 2019 - Google Patents
Abstract Systems and methods for performing multi-message transaction based
performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect …
performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect …
System on a chip comprising multiple compute sub-systems
MB Davis, DJ Borland - US Patent 10,523,585, 2019 - Google Patents
Embodiments can provide additional computing resources at minimal and incremental cost
by providing instances of one or more server compute subsystems on a system-on-chip. The …
by providing instances of one or more server compute subsystems on a system-on-chip. The …
System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology
The present disclosure is directed to system-on-chip (SoC) optimization through
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …
Using multiple traffic profiles to design a network on chip
S Kumar - US Patent 9,294,354, 2016 - Google Patents
9,185,023 2002fOO71392 2002fOO73380 2002fO095430 2004/0216072 2005, 0147081
2006.0161875 2007/01 1832O 2007/0244676 2007/0256O44 2007/026768O 2008 …
2006.0161875 2007/01 1832O 2007/0244676 2007/0256O44 2007/026768O 2008 …
Monitoring and optimizing interhost network traffic
X Qi, F Kavathia, C Raman, S Shah, R Koganty… - US Patent …, 2020 - Google Patents
Some embodiments provide a method for clustering a set of data compute nodes (DCNs),
which communicate with each other more frequently, on one or more host machines. The …
which communicate with each other more frequently, on one or more host machines. The …