Rapid progress in the CMOS technology for the past 25 years has increased the
vulnerability of processors towards faults. Subsequently, focus of computer architects shifted …

Since embedded systems design involves stringent design constraints, designing a system
for reliability requires optimization under tolerable overhead constraints. This paper presents …

In this work, we present an exploration platform for microcoded RISC-V cores leveraging the
One Instruction Set Computer (OISC) principle. Following the industry-proven virtual …

Rapid advancement in deep sub-micron regime has made the integration of multiple
processing elements possible on a single chip. This has enabled parallel execution of …

This paper presents an approach to design and implement a soft-core processor on SRAM-
based FPGAs able to autonomously deal with the occurrence of soft errors; state-of-the-art …

Reliability has taken centre stage in the development of high-performance computing
processors. A Surge of interest is noticeable in recent times in formulating fault and failure …

Occurrences of both transient and permanent errors pose a major challenge in the wake of
burgeoning growth in transistor density. Manufacturing defects and process variants lead to …

Billions of transistors on a chip have led to integration of many cores leading to many
challenges such as increased power dissipation, thermal dissipation, occurrence of faults in …

This work presents a method to reliably perform computations in the presence of both hard
faults arising from aggressive technology scaling and design defects from human error. The …

Integration of multiple processing elements on a single chip has lead to parallel execution of
applications on the same multicore platform. For these applications, task mapping and …