Three-dimensional integrated circuit design
To the observer, it would appear that New York city has a special place in the hearts of
integrated circuit (IC) designers. Manhattan geometries, which mimic the blocks and streets …
integrated circuit (IC) designers. Manhattan geometries, which mimic the blocks and streets …
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon
via (TSV) has gained interest for future SOC integration. Since TSV fill material and silicon …
via (TSV) has gained interest for future SOC integration. Since TSV fill material and silicon …
Yield enhancement for 3D-stacked ICs: Recent advances and challenges
Three-dimensional (3D) integrated circuits (ICs) that stack multiple dies vertically using
through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The …
through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The …
Low-power and reliable clock network design for through-silicon via (TSV) based 3D ICs
This paper focuses on low-power and low-slew clock network design and analysis for
through-silicon via (TSV) based three-dimensional stacked ICs (3D ICs). First, we investigate …
through-silicon via (TSV) based three-dimensional stacked ICs (3D ICs). First, we investigate …
Test-architecture optimization and test scheduling for TSV-based 3-D stacked ICs
B Noia, K Chakrabarty, SK Goel… - … on Computer-Aided …, 2011 - ieeexplore.ieee.org
Through-silicon via (TSV)-based 3-D stacked ICs (SICs) are becoming increasingly
important in the semiconductor industry. In this paper, we address test architecture …
important in the semiconductor industry. In this paper, we address test architecture …
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis
Three-dimensional (3D) ICs promise to overcome barriers in interconnect scaling by
leveraging fast, dense inter-die vias, thereby offering benefits of improved performance …
leveraging fast, dense inter-die vias, thereby offering benefits of improved performance …
TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test
K Chakrabarty, S Deutsch… - 2012 IEEE International …, 2012 - ieeexplore.ieee.org
3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) have emerged as a
promising solution for overcoming interconnect and power bottlenecks in IC design …
promising solution for overcoming interconnect and power bottlenecks in IC design …
TSV-based 3-D ICs: Design methods and tools
Vertically integrated circuits (3-D ICs) may revitalize Moore's law scaling which has slowed
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
Pre-bond and post-bond test and signal recovery structure to characterize and repair TSV defect induced signal degradation in 3-D system
In this paper, we present a methodology for characterization and repair of signal
degradation in through-silicon-vias (TSVs) in 3-D integrated circuits (ICs). The proposed …
degradation in through-silicon-vias (TSVs) in 3-D integrated circuits (ICs). The proposed …
Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system
In this paper we present a test structure and design methodology for testing,
characterization, and self-repair of TSVs in 3D ICs. The proposed structure can detect the …
characterization, and self-repair of TSVs in 3D ICs. The proposed structure can detect the …