[PDF][PDF] Mixed criticality systems-a review

A Burns, R Davis - … of Computer Science, University of York …, 2013 - www-users.york.ac.uk
This review covers research on the topic of mixed criticality systems that has been published
since Vestal's 2007 paper. It covers the period up to end of 2021. The review is organised …

Mixed criticality systems-a review:(february 2022)

A Burns, RI Davis - 2022 - eprints.whiterose.ac.uk
This review covers research on the topic of mixed criticality systems that has been published
since Vestal's 2007 paper. It covers the period up to end of 2021. The review is organised …

[HTML][HTML] The tetrisc soc—a resilient quad-core system based on the resilicell approach

M Ulbricht, L Lu, J Chen, M Krstic - Microelectronics Reliability, 2023 - Elsevier
Resilient systems require monitoring and prediction of environmental and intrinsic
conditions and the ability to adapt to changing circumstances to optimize the trade-off …

Hybrid modular redundancy: Exploring modular redundancy approaches in RISC-V multi-core computing clusters for reliable processing in space

M Rogenmoser, Y Tortorella, D Rossi, F Conti… - ACM Transactions on …, 2023 - dl.acm.org
Space Cyber-Physical Systems (S-CPS) such as spacecraft and satellites strongly rely on
the reliability of onboard computers to guarantee the success of their missions. Relying …

Variable delayed dual-core lockstep (vdcls) processor for safety and security applications

K Marcinek, WA Pleskacz - Electronics, 2023 - mdpi.com
Dual-Core Lockstep (DCLS) is one of the most commonly used techniques in applications
requiring functional safety. As the semiconductor process nodes keep shrinking, the DCLS …

The ZuSE-KI-mobil AI accelerator SOC: overview and a functional safety perspective

F Kempf, J Hoefer, T Harbaum, J Becker… - … , Automation & Test …, 2023 - ieeexplore.ieee.org
ZuSE-KI-Mobil (ZuKIMo) is a nationally funded research project, currently in its intermediate
stage. The goal of the ZuKIMo project is to develop a new System-on-Chip (SoC) platform …

Runtime adaptive cache checkpointing for risc multi-core processors

F Kempf, J Hoefer, F Kreß, T Hotfilter… - 2022 IEEE 35th …, 2022 - ieeexplore.ieee.org
In the future, it is expected that safety-critical and non-critical applications are executed on
the same hardware. Therefore, future hardware systems should be capable of providing …

A survey of recent developments in testability, safety and security of risc-v processors

J Anders, P Andreu, B Becker, S Becker… - 2023 IEEE European …, 2023 - ieeexplore.ieee.org
With the continued success of the open RISC-V architecture, practical deployment of RISC-V
processors necessitates an in-depth consideration of their testability, safety and security …

Distributed voters for automotive applications

M Stoffel, E Sax - 2023 IEEE Intelligent Vehicles Symposium (IV …, 2023 - ieeexplore.ieee.org
Autonomous Vehicles (AVs) operate in public areas without the intervention of a human
driver. This vulnerable environment brings explicit safety requirements to the AV which must …

Leveraging Adaptive Redundancy in Multi-Core Processors for Realizing Adaptive Fault Tolerance in Mixed-Criticality Systems

F Kempf, J Becker - 2023 12th Mediterranean Conference on …, 2023 - ieeexplore.ieee.org
Nowadays, embedded systems are ubiquitous and their functionality is becoming
increasingly intertwined with various critical demands. Integrating functionality with different …