Efficient, dynamic multi-task execution on fpga-based computing systems

UI Minhas, R Woods, DS Nikolopoulos… - … on Parallel and …, 2021 - ieeexplore.ieee.org
With growing Field Programmable Gate Array (FPGA) device sizes and their integration in
environments enabling sharing of computing resources such as cloud and edge computing …

Reconstructing thin structures of manifold surfaces by integrating spatial curves

S Li, Y Yao, T Fang, L Quan - Proceedings of the IEEE …, 2018 - openaccess.thecvf.com
The manifold surface reconstruction in multi-view stereo often fails in retaining thin structures
due to incomplete and noisy reconstructed point clouds. In this paper, we address this …

Dynamic scheduling of task graphs in multi-FPGA systems using critical path

R Ramezani - The Journal of Supercomputing, 2021 - Springer
SRAM-based FPGAs feature high performance and flexibility. Thus, they have found many
applications in modern high-performance computing (HPC) systems. These systems suffer …

Flexible Updating of Internet of Things Computing Functions through Optimizing Dynamic Partial Reconfiguration

G Kornaros, S Leivadaros… - ACM Transactions on …, 2024 - dl.acm.org
With applications to become increasingly compute-and data-intensive, requiring more
processing power, many Internet of Things (IoT) platforms in robots, drones, and …

Hybrid scheduling to enhance reliability of real-time tasks running on reconfigurable devices

A Ghavidel, Y Sedaghat, M Naghibzadeh - The Journal of …, 2020 - Springer
Reconfigurable devices (RDs) are extremely advantageous when employed in real-time
embedded systems. Nonetheless, they are susceptible to soft errors. In a broad sense, the …

Dynamic placement optimization for bio-inspired self-repairing hardware

L Xiubin, Q Yanling, F Xiangli, Z Qingqi, L Yue - IEEE Access, 2020 - ieeexplore.ieee.org
Bio-inspired self-repairing hardware is a distributed self-adaptive system, characterized by
powerful fault-tolerant ability and environment adaptivity. However, it suffers from some …

A decomposition-based reliability and makespan optimization technique for hardware task graphs

R Ramezani, Y Sedaghat, M Naghibzadeh… - Reliability Engineering & …, 2018 - Elsevier
This paper presents an approach to optimize the reliability and makespan of hardware task
graphs, running on FPGA-based reconfigurable computers, in space-mission computing …

Resource provisioning framework for CPU-FPGA environments with adaptive and synergistic HLS-versioning and DVFS

MG Jordan - 2023 - lume.ufrgs.br
Cloud companies have been exploiting CPU-FPGA collaborative environments to accel
erate multi-tenant task requests with scalability and maximize resource utilization. In this …

Design of distributed timing task scheduling system for smart grid

WS Tang, JZ Wang, T Fan - Journal of Physics: Conference …, 2021 - iopscience.iop.org
With the rapid development of information technology and the growing scale of enterprise
development, more and more enterprise application systems appear due to business …

Work-in-progress: Design space exploration of multi-task processing on space shared FPGAs

UI Minhas, R Woods… - … Conference on Hardware …, 2019 - ieeexplore.ieee.org
High level synthesis frameworks, such as OpenCL, allow effective design space exploration
by scaling of resource allocation via simple to use tunable parameters. The same process …