Nanoionic memristive phenomena in metal oxides: the valence change mechanism

R Dittmann, S Menzel, R Waser - Advances in Physics, 2021 - Taylor & Francis
This review addresses resistive switching devices operating according to the bipolar
valence change mechanism (VCM), which has become a major trend in electronic materials …

Resistive random access memory: a review of device challenges

V Gupta, S Kapur, S Saurabh, A Grover - IETE Technical Review, 2020 - Taylor & Francis
With scaling, existing charge-based memory technologies exhibit limitations due to charge
leaking away easily in a smaller device. Therefore, non-charge based memory technologies …

Microscopic Modeling of HfOx RRAM Operations: From Forming to Switching

A Padovani, L Larcher, O Pirrotta… - … on electron devices, 2015 - ieeexplore.ieee.org
We propose a model describing the operations of hafnium oxide-based resistive random
access memory (RRAM) devices at the microscopic level. Charge carrier and ion transport …

Highly uniform resistive switching characteristics of Ti/TaOx/ITO memristor devices for neuromorphic system

D Ju, JH Kim, S Kim - Journal of Alloys and Compounds, 2023 - Elsevier
In this study, we focused on the uniformity of resistance states of Ti/TaO x/ITO devices and
the possibility of using them in neuromorphic applications under DC and pulse …

Direct measurement of nanoscale filamentary hot spots in resistive memory devices

S Deshmukh, MM Rojo, E Yalon, S Vaziri… - Science …, 2022 - science.org
Resistive random access memory (RRAM) is an important candidate for both digital, high-
density data storage and for analog, neuromorphic computing. RRAM operation relies on …

ZnO and ZnO-based materials as active layer in resistive random-access memory (RRAM)

E Nowak, E Chłopocka, M Szybowicz - Crystals, 2023 - mdpi.com
In this paper, an overview of the influence of various modifications on ZnO-based RRAM has
been conducted. Firstly, the motivation for creating new memory technology is presented …

Device-aware test: A new test approach towards DPPB level

M Fieback, L Wu, GC Medeiros, H Aziza… - 2019 IEEE …, 2019 - ieeexplore.ieee.org
This paper proposes a new test approach that goes beyond cell-aware test, ie, device-aware
test. The approach consists of three steps: defect modeling, fault modeling, and test/DfT …

Defects, fault modeling, and test development framework for RRAMs

M Fieback, GC Medeiros, L Wu, H Aziza… - ACM Journal on …, 2022 - dl.acm.org
Resistive RAM (RRAM) is a promising technology to replace traditional technologies such
as Flash, because of its low energy consumption, CMOS compatibility, and high density …

Toward reliable multi-level operation in RRAM arrays: Improving post-algorithm stability and assessing endurance/data retention

E Perez, C Zambelli, MK Mahadevaiah… - IEEE Journal of the …, 2019 - ieeexplore.ieee.org
Achieving a reliable multi-level operation in resistive random access memory (RRAM) arrays
is currently a challenging task due to several threats like the post-algorithm instability …

Multilevel cell storage and resistance variability in resistive random access memory

A Prakash, H Hwang - Physical Sciences Reviews, 2016 - degruyter.com
Multilevel per cell (MLC) storage in resistive random access memory (ReRAM) is attractive
in achieving high-density and low-cost memory and will be required in future. In this chapter …