Systems and methods for facilitating low power on a network-on-chip
JA Bauman, J Rowlands, S Kumar - US Patent 10,452,124, 2019 - Google Patents
Aspects of the present disclosure are directed to a power specification and Network on Chip
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …
System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology
The present disclosure is directed to system-on-chip (SoC) optimization through
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …
Generating physically aware network-on-chip design from a physical system-on-chip specification
R Chopra, YT Lin, S Kumar - US Patent 10,218,580, 2019 - Google Patents
Different example implementations of the present disclosure relates to methods and
computer readable mediums for automatically generating physically aware NoC design and …
computer readable mediums for automatically generating physically aware NoC design and …
Generation of network-on-chip layout based on user specified topological constraints
PG Raponi, E Norige, S Kumar - US Patent 10,050,843, 2018 - Google Patents
In an aspect, the present disclosure provides a method that comprises automatic generation
of a NoC from specified topological information based on projecting NoC elements of the …
of a NoC from specified topological information based on projecting NoC elements of the …
Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA)
S Kumar - US Patent 11,023,377, 2021 - Google Patents
Methods and example implementations described herein are generally directed to the
addition of networks-on-chip (NoC) to FPGAs to customize traffic and optimize performance …
addition of networks-on-chip (NoC) to FPGAs to customize traffic and optimize performance …
Repository of integration description of hardware intellectual property for NoC construction and SoC integration
Methods and example implementations described herein are generally directed to
repository of integration description of hardware intellectual property (IP) for NoC …
repository of integration description of hardware intellectual property (IP) for NoC …
Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation
(57) ABSTRACT A system and method for automatic crossbar generation and router
connections for Network-on-Chip (NoC) topology generation is disclosed. Aspects of the …
connections for Network-on-Chip (NoC) topology generation is disclosed. Aspects of the …
Streaming bridge design with host interfaces and network on chip (NoC) layers
R Chopra, S Kumar - US Patent 10,084,692, 2018 - Google Patents
Abstract Systems and methods described herein are directed to streaming bridge design
implementations that help interconnect and transfer transaction packets between multiple …
implementations that help interconnect and transfer transaction packets between multiple …
Shared memory mesh for switching
KS Papadantonakis, R Southworth… - US Patent …, 2023 - Google Patents
2019-10-22 Assigned to INTEL CORPORATION reassignment INTEL CORPORATION
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Cost management against requirements for the generation of a NoC
Example implementations as described herein are directed to systems and methods for
processing a NoC specification for a plurality of performance requirements of a NoC, and …
processing a NoC specification for a plurality of performance requirements of a NoC, and …