The placement stage of the physical design of very large-scale integrated circuits (VLSI)
specifies the arrangement and order of standard cells and devices within an area, and the …

The paper is devoted to the issues of modeling objects and processes at various stages of
designing the layout of microelectronic devices. Geometric two-dimensional models of …

As semiconductor manufacturing moves into the nanotechnology era, mixed-size standard
cell circuit designs have become mainstream, but they also pose significant challenges to …

With the development of advanced process technology, the electrical characteristic variation
of MOSFET transistors has been seriously influenced by layout dependent effect (LDEs) …

In traditional circuit designs, rows within the placement region typically have uniform height.
However, a novel hybrid-row-height design paradigm has recently emerged, integrating tall …

Статья посвящена рассмотрению вопросов моделирования объектов и процессов на
различных этапах проектирования топологии микроэлектронных устройств …