This paper proposes a low-power design method and a low-noise phase offset calibration
technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally …

In this article, we propose a digital-to-time conversion technique operating entirely in the
sinusoidal waveform voltage domain of a crystal oscillator (XO) before the signal's final …

This article presents a 7-GHz fractional-N digital phase-locked loop (DPLL) without any
digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter …

This letter describes a fully synthesizable fractional-multiplexing delay-locked loop (MDLL)
with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can …

This work presents a fractional-N digital phase-locked loop (DPLL) characterized by low
jitter and small area, featuring fast multi-variable calibration. To minimize the use of silicon …

This article presents a ring voltage-controlled oscillator (RVCO)-based pulse-injection-
locked clock multiplier (ILCM) with a complementary-injection scheme, an adaptive …

A phase-locked loop (PLL) employing a split-feedback divider and nested-PLL-based phase-
domain low-pass filter (PDLPF) within the harmonic-mixer (HM)-based dual-feedback …

This work presents a multiplying delay-locked loop (MDLL) that can generate an ultralow
jitter output signal,, at a very high output frequency,. Conventional MDLLs are limited in …

This article examines the research area of digital phase-locked loops (DPLLs), a critical
component in modern electronic systems, from wireless communication devices to RADAR …

This brief proposes a 7.4–9.2-GHz low-noise fractional-N differential sampling phase-locked
loop (DSPLL), which features doubled phase detector (PD) gain. By using the phase …