Review of the nanoscale FinFET device for the applications in nano-regime
Background: The insatiable need for low-power and high-performance integrated circuit (IC)
results in the development of alternative options for metal oxide semiconductor field effect …
results in the development of alternative options for metal oxide semiconductor field effect …
Design optimization of three-stacked nanosheet FET from self-heating effects perspective
Self-heating effect (SHE) is a severe issue arising in the nanoscale field-effect transistors
(FETs). It raises the device's lattice temperature several degrees higher than the ambient …
(FETs). It raises the device's lattice temperature several degrees higher than the ambient …
Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques
One of the severe issues of the downscaling of semiconductor devices is the threshold
voltage reduction which significantly increases the leakage current. Thus, high threshold …
voltage reduction which significantly increases the leakage current. Thus, high threshold …
Multi- Strategies of 7-nm node Nanosheet FETs With Limited Nanosheet Spacing
In this paper, multi-threshold voltage (V th) scheme of 7-nm node nanosheet FETs (NSFETs)
with narrow NS spacing were successfully achieved by metal-gate work function (WF) and …
with narrow NS spacing were successfully achieved by metal-gate work function (WF) and …
PVT-aware design of dopingless dynamically configurable tunnel FET
This paper presents a new design of dopingless dynamically configurable double-gate
tunnel FET (TFET) for process-voltage-temperature (PVT)-aware applications. The …
tunnel FET (TFET) for process-voltage-temperature (PVT)-aware applications. The …
Analog/RF and linearity performance assessment of a negative capacitance FinFET using high threshold voltage techniques
The continued exploration of the ferroelectric-based negative capacitance field effect
transistor (NCFET) for energy-efficient and higher current drivability merits has called for an …
transistor (NCFET) for energy-efficient and higher current drivability merits has called for an …
Impact of process variation on nanosheet gate-all-around complementary FET (CFET)
X Yang, X Li, Z Liu, Y Sun, Y Liu, X Li… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this work, dc characteristic variations of nanosheet (NS) gate-all-around (GAA)
complementary FET (CFET) induced by process fluctuations are investigated for the first …
complementary FET (CFET) induced by process fluctuations are investigated for the first …
Deep learning algorithms for the work function fluctuation of random nanosized metal grains on gate-all-around silicon nanowire MOSFETs
Device simulation has been explored and industrialized for over 40 years; however, it still
requires huge computational cost. Therefore, it can be further advanced using deep learning …
requires huge computational cost. Therefore, it can be further advanced using deep learning …
Design and optimization of triple-k spacer structure in two-stack nanosheet FET from OFF-state leakage perspective
In this article, a 5-nm node two-stack nanosheet FET with a triple-k spacer structure
representing three spacer regions consisting of two inner spacers (inner spacer 1 and inner …
representing three spacer regions consisting of two inner spacers (inner spacer 1 and inner …
3-D LER and RDF matching performance of nanowire FETs in inversion, accumulation, and junctionless modes
Nanowire field-effect transistors (NWFETs) have emerged as promising candidates for
realization of advanced CMOS technology nodes. Due to small nanowire dimensions …
realization of advanced CMOS technology nodes. Due to small nanowire dimensions …