Transistor count reduction by gate merging
CM de Oliveira Conceição… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
A large set of ASICs uses much more transistors than its necessity, as they use a library of
cells with a limited amount of logic functions. This small number of logic functions in a …
cells with a limited amount of logic functions. This small number of logic functions in a …
Simultaneous two-dimensional cell layout compaction using milp with astran
AM Ziesemer, RA da Luz Reis - 2014 IEEE Computer Society …, 2014 - ieeexplore.ieee.org
This paper describes a technique to compact cell layouts efficiently using Mixed-Integer
Linear Programming. By using binary variables we were able not only to model the …
Linear Programming. By using binary variables we were able not only to model the …
Mining system-user interaction traces for use case models
M El-Ramly, E Stroulia… - … International Workshop on …, 2002 - ieeexplore.ieee.org
While code understanding is the primary program comprehension activity, it is quite
challenging to recognize the application requirements from code, since they have usually …
challenging to recognize the application requirements from code, since they have usually …
ASCEnD-FreePDK45: An open source standard cell library for asynchronous design
An analysis of the state of art in asynchronous circuits reveals a lack of resources to support
their design. When asynchronous cell libraries appear in the literature, they often …
their design. When asynchronous cell libraries appear in the literature, they often …
Automated synthesis of cell libraries for asynchronous circuits
Asynchronous techniques are regaining relevance in the VLSI research community as they
allow increasing robustness against process variability considerably, by relaxing timing …
allow increasing robustness against process variability considerably, by relaxing timing …
Physical design automation of transistor networks
AM Ziesemer Jr, R Reis - Microelectronic Engineering, 2015 - Elsevier
Integrated circuits implemented with traditional standard cell approaches use a limited set of
cells available in a library, created in advance, to generate its layout. It breaks complexity but …
cells available in a library, created in advance, to generate its layout. It breaks complexity but …
Asynchronous circuits: innovations in components, cell libraries and design templates
MT Moreira - 2016 - meriva.pucrs.br
For decades now, the synchronous paradigm has been the major choice of the industry for
building integrated circuits. Unfortunately, with the development of semiconductor industry …
building integrated circuits. Unfortunately, with the development of semiconductor industry …
Perfomance improvement with dedicated transistor sizing for mosfet and finfet devices
G Posser, J Belomo, C Meinhardt… - 2014 IEEE Computer …, 2014 - ieeexplore.ieee.org
This work presents a transistor sizing tool to optimize performance taking into account area
and power consumption in MOSFET and FinFET devices. The sizing tool is based on …
and power consumption in MOSFET and FinFET devices. The sizing tool is based on …
Electrical and Physical Evaluation of Logic Network Generation Methods for SCCG
JP Ramírez, CS Cárdenas - 2023 IEEE 66th International …, 2023 - ieeexplore.ieee.org
The digital integrated circuit implementation strategies in the microelectronics industry have
changed over the years considering the design costs. Hand design flows have been …
changed over the years considering the design costs. Hand design flows have been …
Topological characteristics of logic networks generated by a graph-based methodology
MS Cardoso, R Zanandrea… - 2016 IEEE 7th Latin …, 2016 - ieeexplore.ieee.org
Graph-based methodologies for supergate design have gained relevance recently. Due to
the non-series-parallel arrangements and the transistor sharing technique, these …
the non-series-parallel arrangements and the transistor sharing technique, these …