Method and system for open loop compensation of delay variations in a delay line
SV Shinde - US Patent 8,390,356, 2013 - Google Patents
The present invention provides a method and system for open loop compensation of delay
variations in a delay line. The method includes sensing the Process, Voltage, Temperature …
variations in a delay line. The method includes sensing the Process, Voltage, Temperature …
Semiconductor device having a mismatch detection and correction circuit
JS Kim, SH Kim, KH Kim - US Patent 10,310,536, 2019 - Google Patents
A semiconductor device includes: an integrated circuit (IC) including an internal circuit; and
a mismatch detection and correction circuit connected to the internal circuit of the IC, the …
a mismatch detection and correction circuit connected to the internal circuit of the IC, the …
Control circuit and delay circuit
L Zhu - US Patent 11,528,020, 2022 - Google Patents
The feedback unit is configured to output a feedback signal according to a voltage of the
control unit and a reference voltage; a first terminal of the feedback unit is connected to a first …
control unit and a reference voltage; a first terminal of the feedback unit is connected to a first …
Methods and apparatus for power reduction in a transceiver
PS Gudem, SC Ciccarelli, KTK Mok… - US Patent 8,565,669, 2013 - Google Patents
US8565669B2 - Methods and apparatus for power reduction in a transceiver - Google Patents
US8565669B2 - Methods and apparatus for power reduction in a transceiver - Google Patents …
US8565669B2 - Methods and apparatus for power reduction in a transceiver - Google Patents …
Method and apparatus for regulating a power supply of an integrated circuit
K Azimi, MS Mobin, GW Sheets, LA Smith - US Patent 8,081,011, 2011 - Google Patents
US8081011B2 - Method and apparatus for regulating a power supply of an integrated circuit -
Google Patents US8081011B2 - Method and apparatus for regulating a power supply of an …
Google Patents US8081011B2 - Method and apparatus for regulating a power supply of an …
Voltage generating circuit, inverter, delay circuit, and logic gate circuit
L Zhu - US Patent 11,681,313, 2023 - Google Patents
G05F1/00—Automatic systems in which deviations of an electric quantity from one or more
predetermined values are detected at the output of the system and fed back to a device …
predetermined values are detected at the output of the system and fed back to a device …
2× VDD-tolerant logic circuits and a related 2× VDD-tolerant I/O buffer with PVT compensation
A 2× VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature
(PVT) compensation suitable for CMOS technology is disclosed. A 2× VDD-tolerant I/O buffer …
(PVT) compensation suitable for CMOS technology is disclosed. A 2× VDD-tolerant I/O buffer …
Circuit for and method of determining a process corner for a CMOS device
GJ Ren - US Patent 8,146,036, 2012 - Google Patents
(57) ABSTRACT A circuit for determining a process corner for a CMOS device of an
integrated circuit is disclosed. The circuit comprises a CMOS monitoring circuit comprising …
integrated circuit is disclosed. The circuit comprises a CMOS monitoring circuit comprising …
2× VDD-tolerant logic circuits and a related 2× VDD-tolerant I/O buffer with PVT compensation
(57) ABSTRACT A 2xVDD-tolerant input/output (I/O) buffer circuit with pro cess, Voltage, and
temperature (PVT) compensation Suitable for CMOS technology is disclosed. A 2xVDD …
temperature (PVT) compensation Suitable for CMOS technology is disclosed. A 2xVDD …
Method and apparatus for regulating a power supply of an integrated circuit
K Azimi, MS Mobin, GW Sheets, LA Smith - US Patent 7,791,368, 2010 - Google Patents
US7791368B2 - Method and apparatus for regulating a power supply of an integrated
circuit - Google Patents US7791368B2 - Method and apparatus for regulating a power …
circuit - Google Patents US7791368B2 - Method and apparatus for regulating a power …