Nonvolatile memory with write cache having flush/eviction methods
A Paley, SA Gorobets, E Zilberman, AD Bennett… - US Patent …, 2014 - Google Patents
A portion of a nonvolatile memory is partitioned from a main multi-level memory array to
operate as a cache. The cache memory is configured to store at less capacity per memory …
operate as a cache. The cache memory is configured to store at less capacity per memory …
Container marker scheme for reducing write amplification in solid state devices
A solid state storage device and method are provided. Multiple blocks are configured as
storage memory for a solid state storage device, and each block includes multiple pages. A …
storage memory for a solid state storage device, and each block includes multiple pages. A …
A survey of techniques for architecting slc/mlc/tlc hybrid flash memory–based ssds
Flash memory–based solid‐state drives (SSDs) offer several attractive features and benefits
compared to hard disk drive (HDD), such as shock resistance and better performance …
compared to hard disk drive (HDD), such as shock resistance and better performance …
Wear leveling of multiple memory devices
MA d'Abreu, S Skala - US Patent 9,208,070, 2015 - Google Patents
A method of managing wear leveling in a data storage device includes determining whether
a reliability measurement associated with a first portion of a first nonvolatile memory die …
a reliability measurement associated with a first portion of a first nonvolatile memory die …
Memory system performing wear leveling based on deletion request
D Hashimoto - US Patent 9,026,764, 2015 - Google Patents
(57) ABSTRACT A memory system of a embodiments includes a first storing area having
physical blocks and a second storing area record ing a logical to physical translation table …
physical blocks and a second storing area record ing a logical to physical translation table …
Smart bridge for memory core
MA d'Abreu, S Skala, D Pantelakis, R Nair… - US Patent …, 2015 - Google Patents
(57) ABSTRACT Jul. 26, 2011 (IN)......................... 2124/MUMA2011 aaaS 1CUCS a S COW
C1 1CTUC19 a TIS An apparatu lud first ry d luding a first (51) Int. Cl. memory core, a …
C1 1CTUC19 a TIS An apparatu lud first ry d luding a first (51) Int. Cl. memory core, a …
Memory system and method for controlling a nonvolatile semiconductor memory
J Yano, K Hatsuda, H Matsuzaki, W Okamoto - US Patent 8,745,313, 2014 - Google Patents
(57) ABSTRACT A memory system includes a nonvolatile semiconductor memory having
blocks, the block being data erasing unit; and a controller configured to execute; an update …
blocks, the block being data erasing unit; and a controller configured to execute; an update …
Memory system with write coalescing
J Yano, H Matsuzaki, K Hatsuda - US Patent 7,904,640, 2011 - Google Patents
(57) ABSTRACT A controller executes first processing for writing a plurality of data in a
sector unit in the first storing area; second processing for flushing the data stored in the first …
sector unit in the first storing area; second processing for flushing the data stored in the first …
Memory system for flushing and relocating data
J Yano, H Matsuzaki, K Hatsuda, W Okamoto… - US Patent …, 2012 - Google Patents
(57) ABSTRACT A system includes: a first input buffer that functions as an input buffer for a
third storing area; and a second input buffer that functions as an input buffer for the third …
third storing area; and a second input buffer that functions as an input buffer for the third …
Smart bridge for memory core
MA d'Abreu, S Skala, D Pantelakis, R Nair… - US Patent …, 2016 - Google Patents
US9406346B2 - Smart bridge for memory core - Google Patents US9406346B2 - Smart bridge
for memory core - Google Patents Smart bridge for memory core Download PDF Info Publication …
for memory core - Google Patents Smart bridge for memory core Download PDF Info Publication …