Flexible setup for the measurement of CMOS time-dependent variability with array-based integrated circuits

J Diaz-Fortuny, P Saraza-Canflanca… - IEEE Transactions …, 2019 - ieeexplore.ieee.org
This paper presents an innovative and automated measurement setup for the
characterization of variability effects in CMOS transistors using array-based integrated …

TARS: A toolbox for statistical reliability modeling of CMOS devices

J Diaz-Fortuny, J Martín-Martínez… - … and Applications to …, 2017 - ieeexplore.ieee.org
This paper presents a toolbox for the automation of the electrical characterization of CMOS
transistors. The developed software provides a user-friendly interface to carry out different …

A model parameter extraction methodology including time-dependent variability for circuit reliability simulation

J Diaz-Fortuny, P Saraza-Canflanca… - … and Applications to …, 2018 - ieeexplore.ieee.org
In current CMOS advanced technology nodes, accurate extraction of transistor parameters
affected by time-dependent variability, like threshold voltage (Vth) and mobility (μ), has …

Statistical threshold voltage shifts caused by BTI and HCI at nominal and accelerated conditions

J Diaz-Fortuny, P Saraza-Canflanca, R Rodriguez… - Solid-State …, 2021 - Elsevier
In nowadays deeply scaled CMOS technologies, time-zero and time-dependent variability
effects have become important concerns for analog and digital circuit design. For instance …

[HTML][HTML] An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage

J Diaz-Fortuny, P Saraza-Canflanca, E Bury… - Micromachines, 2024 - mdpi.com
The reliability and durability of integrated circuits (ICs), present in almost every electronic
system, from consumer electronics to the automotive or aerospace industries, have been …

Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability

VM Van Santen, J Diaz-Fortuny… - 2018 IEEE …, 2018 - ieeexplore.ieee.org
Recent MOSFET devices exhibit a strong variability in their Bias Temperature Instability (BTI)
induced degradation (eg, Vth-shift). For identical stress patterns, each device exhibits …

A smart noise-and RTN-removal method for parameter extraction of CMOS aging compact models

J Diaz-Fortuny, J Martin-Martinez, R Rodriguez… - Solid-State …, 2019 - Elsevier
In modern nanometer-scale CMOS technologies, time-zero and time-dependent variability
(TDV) effects, the latter coming from aging mechanisms like Bias Temperature Instability …

Design considerations of an SRAM array for the statistical validation of time-dependent variability models

P Saraza-Canflanca, D Malagon… - … and Applications to …, 2018 - ieeexplore.ieee.org
Modeling and characterization of time-dependent variability phenomena as well as the
simulation of their impact on circuit operation have attracted considerable efforts. This paper …

New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors

P Saraza-Canflanca, J Diaz-Fortuny… - … , Automation & Test …, 2019 - ieeexplore.ieee.org
Bias Temperature Instability has become a critical issue for circuit reliability. This
phenomenon has been found to have a stochastic and discrete nature in nanometer-scale …

Advanced characterization and analysis of random telegraph noise in CMOS devices

J Martin-Martinez, R Rodriguez, M Nafria - Noise in Nanoscale …, 2020 - Springer
RTN is one of the most relevant time-dependent variability sources and, as such, must be
taken into account during the design of memories, digital and analog VLSI-integrated circuits …