Impact of single-event upsets on convolutional neural networks in Xilinx Zynq FPGAs
HB Wang, YS Wang, JH Xiao… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Convolutional neural networks (CNNs) are quickly becoming an attractive solution for
autonomous vehicles, military weapons, and space exploration. Thanks to their …
autonomous vehicles, military weapons, and space exploration. Thanks to their …
DMBF: Design metrics balancing framework for soft-error-tolerant digital circuits through bayesian optimization
Radiation Hardened by Design (RHBD) is one of the main measures for solving the soft
error issue in digital circuits. However, a multi-objective optimization (MOO) problem …
error issue in digital circuits. However, a multi-objective optimization (MOO) problem …
Innovative leakage stabilization system for mitigation of ionizing radiation-induced effects
S Anjankar, R Dhavse - IEEE Sensors Letters, 2023 - ieeexplore.ieee.org
In this letter, a novel radiation leakage stabilization circuit (LSC) using Semi-Conductor
Laboratory (SCL) 180-nm metal oxide semiconductor capacitor technology-based ionizing …
Laboratory (SCL) 180-nm metal oxide semiconductor capacitor technology-based ionizing …
Design and analysis of soft error rate in FET/CNTFET based radiation hardened SRAM cell
BR Muthu, EP Pushpa, V Dhandapani, K Jayaraman… - Sensors, 2021 - mdpi.com
Aerospace equipages encounter potential radiation footprints through which soft errors
occur in the memories onboard. Hence, robustness against radiation with reliability in …
occur in the memories onboard. Hence, robustness against radiation with reliability in …
Comparison of total ionizing dose effect on tolerance of SCL 180 nm bulk and SOI CMOS using TCAD simulation
S Anjankar, R Dhavse - … and Networking: Select Proceedings of the Fourth …, 2022 - Springer
The long-term reliability of metal oxide semiconductor (MOS) devices in space technology
depends on the total ionizing dose (TID) effect. In MOS technology, power consuming …
depends on the total ionizing dose (TID) effect. In MOS technology, power consuming …
A universal, low-delay, SEC-DEC-TAEC code for state register protection
M Dong, W Pan, Z Qiu, X Qi, L Zheng, H Liu - IEEE Access, 2022 - ieeexplore.ieee.org
Finite State Machine (FSM) is widely used in electronic systems and its reliability is critical to
the system. Ionizing radiation induced soft error is one of the major concerns in the design of …
the system. Ionizing radiation induced soft error is one of the major concerns in the design of …
A low-overhead FFT design with higher SEU resilience implemented in FPGA
HB Wang, YS Wang, JL Cui, SL Wang… - … on Nuclear Science, 2020 - ieeexplore.ieee.org
For area and power constraint applications in mission critical systems, the traditional fast
Fourier transform (FFT) design requires huge hardware resources for data processing. In …
Fourier transform (FFT) design requires huge hardware resources for data processing. In …
[PDF][PDF] The effects of race conditions when implementing single-source redundant clock trees in triple modular redundant synchronous architectures
MD Berg, HS Kim, AM Phan, CM Seidleck… - Radiation Effects on …, 2016 - ntrs.nasa.gov
The Effects of Race Conditions when Implementing Single-Source Redundant Clock Trees in
Triple Modular Redundant Synchronous Arc Page 1 To be published in the 2016 Radiation …
Triple Modular Redundant Synchronous Arc Page 1 To be published in the 2016 Radiation …
Self-correcting Flip-flops for Triple Modular Redundant Logic in a 12-nm Technology
LT Clark, A Duvnjak, C Young-Sciortino… - … on Circuits and …, 2022 - ieeexplore.ieee.org
Area efficient self-correcting flip-flops for use with triple modular redundant (TMR) soft-error
hardened logic are implemented in a 12-nm finFET process technology. The TMR flip-flop …
hardened logic are implemented in a 12-nm finFET process technology. The TMR flip-flop …
A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design
H Wu, G Jin, Y Zhuang, W Cao, L Bai - IEICE Electronics Express, 2021 - jstage.jst.go.jp
A power-efficient Single Event Upset (SEU)-tolerant pulsetriggered flip-flop design is
presented. The dual-modular redundant design takes advantage of concise formation of …
presented. The dual-modular redundant design takes advantage of concise formation of …