Recent thermal management techniques for microprocessors

J Kong, SW Chung, K Skadron - ACM Computing Surveys (CSUR), 2012 - dl.acm.org
Microprocessor design has recently encountered many constraints such as power, energy,
reliability, and temperature. Among these challenging issues, temperature-related issues …

A survey of chip-level thermal simulators

H Sultan, A Chauhan, SR Sarangi - ACM Computing Surveys (CSUR), 2019 - dl.acm.org
Thermal modeling and simulation have become imperative in recent years owing to the
increased power density of high performance microprocessors. Temperature is a first-order …

[PDF][PDF] A case for thermal-aware floorplanning at the microarchitectural level

K Sankaranarayanan, S Velusamy, M Stan… - Journal of Instruction …, 2005 - academia.edu
In current day microprocessors, exponentially increasing power densities, leakage, cooling
costs, and reliability concerns have resulted in temperature becoming a first class design …

3D floorplanning with thermal vias

E Wong, SK Lim - Proceedings of the Design Automation & …, 2006 - ieeexplore.ieee.org
3D circuits have the potential to improve performance over traditional 2D circuits by reducing
wirelength and interconnect delay. One major problem with 3D circuits is that their higher …

Multiobjective microarchitectural floorplanning for 2-D and 3-D ICs

M Healy, M Vittes, M Ekpanyapong… - … on Computer-Aided …, 2006 - ieeexplore.ieee.org
This paper presents the first multiobjective microarchitectural floorplanning algorithm for
high-performance processors implemented in two-dimensional (2-D) and three-dimensional …

Temperature-aware task allocation and scheduling for embedded multiprocessor systems-on-chip (MPSoC) design

Y Xie, WL Hung - Journal of VLSI signal processing systems for signal …, 2006 - Springer
Temperature affects not only the performance but also the power, reliability, and cost of the
embedded system. This paper proposes a temperature-aware task allocation and …

[PDF][PDF] Temperature aware floorplanning

Y Han, I Koren, CA Moritz - Workshop on Temperature Aware …, 2005 - researchgate.net
Power density of microprocessors is increasing with every new process generation resulting
in increasingly higher maximum chip temperatures. The high temperature of the chip greatly …

Thermal-aware task allocation and scheduling for embedded systems

WL Hung, Y Xie, N ViJ'aykrishnan… - … Automation and Test …, 2005 - ieeexplore.ieee.org
Temperature affects not only the reliability but also the performance, power, and cost of the
embedded system. This paper proposes a thermal-aware task allocation and scheduling …

Thermal-aware non-slicing VLSI floorplanning using a smart decision-making PSO-GA based hybrid algorithm

P Sivaranjani, A Senthil Kumar - Circuits, Systems, and Signal Processing, 2015 - Springer
Floorplanning is an important physical design step in the ASIC design flow. It is the process
of estimating the area to be occupied by various blocks in a layout together with a precise …

An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning

J Shanthi, DGN Rani, S Rajaram - Integration, 2022 - Elsevier
Floorplanning is an ever-emerging field in the Very Large Scale Integration (VLSI) circuit
design automation since it deals with essential design metrics of a floorplan, such as chip …