Branch predictor (BP) is an essential component in modern processors since high BP
accuracy can improve performance and reduce energy by decreasing the number of …

It is now widely admitted that in order to provide state-of-the-art accuracy, a conditional
branch predictor must combine several predictions. Recent research has shown that an …

This paper presents BOOM version 2, an updated version of the Berkeley Out-of-Order
Machine first presented in [3]. The design exploration was performed through synthesis …

One architectural method for increasing processor performance involves increasing the
frequency by implementing deeper pipelines. This paper will explore the relationship …

Virtual machines (VMs) enable the distribution of programs in an architecture-neutral format,
which can easily be interpreted or compiled. A long-running question in the design of VMs is …

This paper presents the Alpha EV8 conditional branch predictor The Alpha EV8
microprocessor project, canceled in June 2001 in a late phase of development, envisioned …

A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-
core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently …

Instruction supply is a crucial component of processor performance. Instruction prefetching
has been proposed as a mechanism to help reduce instruction cache misses, which in turn …

Modern microprocessors employ increasingly complicated branch predictors to achieve
instruction fetch bandwidth that is sufficient for wide out-of-order execution cores. While …

In the pursuit of instruction-level parallelism, significant demands are placed on a
processor's instruction delivery mechanism. Delivering the performance necessary to meet …