[图书][B] A primer on memory consistency and cache coherence
Many modern computer systems and most multicore chips (chip multiprocessors) support
shared memory in hardware. In a shared memory system, each of the processor cores may …
shared memory in hardware. In a shared memory system, each of the processor cores may …
TRANSIT: specifying protocols with concolic snippets
With the maturing of technology for model checking and constraint solving, there is an
emerging opportunity to develop programming tools that can transform the way systems are …
emerging opportunity to develop programming tools that can transform the way systems are …
DeNovo: Rethinking the memory hierarchy for disciplined parallelism
B Choi, R Komuravelli, H Sung… - 2011 International …, 2011 - ieeexplore.ieee.org
For parallelism to become tractable for mass programmers, shared-memory languages and
environments must evolve to enforce disciplined practices that ban" wild shared-memory …
environments must evolve to enforce disciplined practices that ban" wild shared-memory …
Token coherence: Decoupling performance and correctness
Many future shared-memory multiprocessor servers will both target commercial workloads
and use highly-integrated" glueless" designs. Implementing low-latency cache coherence in …
and use highly-integrated" glueless" designs. Implementing low-latency cache coherence in …
Complexity-effective multicore coherence
Much of the complexity and overhead (directory, state bits, invalidations) of a typical
directory coherence implementation stems from the effort to make it" invisible" even to the …
directory coherence implementation stems from the effort to make it" invisible" even to the …
Concordia: Distributed shared memory with {In-Network} cache coherence
Distributed shared memory (DSM) is experiencing a resurgence with emerging fast network
stacks. Caching, which is still needed for reducing frequent remote access and balancing …
stacks. Caching, which is still needed for reducing frequent remote access and balancing …
System and method for simplifying cache coherence using multiple write policies
Abstract System and methods for cache coherence in a multi-core processing environment
having a local/shared cache hierarchy. The system includes multiple processor cores, a …
having a local/shared cache hierarchy. The system includes multiple processor cores, a …
A risc-v simulator and benchmark suite for designing and evaluating vector architectures
Vector architectures lack tools for research. Consider the gem5 simulator, which is possibly
the leading platform for computer-system architecture research. Unfortunately, gem5 does …
the leading platform for computer-system architecture research. Unfortunately, gem5 does …
Directed test generation for validation of cache coherence protocols
Computing systems utilize multicore processors with complex cache coherence protocols to
meet the increasing need for performance and energy improvement. It is a major challenge …
meet the increasing need for performance and energy improvement. It is a major challenge …
The Cray BlackWidow: a highly scalable vector multiprocessor
D Abts, A Bataineh, S Scott, G Faanes… - Proceedings of the …, 2007 - dl.acm.org
This paper describes the system architecture of the Cray BlackWidow scalable vector
multiprocessor. The BlackWidow system is a distributed shared memory (DSM) architecture …
multiprocessor. The BlackWidow system is a distributed shared memory (DSM) architecture …