Reliability analysis of a fault-tolerant RISC-V system-on-chip

DA Santos, LM Luza, L Dilillo, CA Zeferino… - Microelectronics …, 2021 - Elsevier
The space environment's hostility requires that the processors used in spacecraft be
designed using fault tolerance techniques to reduce the propagation of errors. In this …

A survey on two-dimensional Error Correction Codes applied to fault-tolerant systems

D Freitas, C Marcon, J Silveira, L Naviner… - Microelectronics …, 2022 - Elsevier
The number of memory faults operating in radiation environments increases with the
electronic device miniaturization. One-dimensional (1D) Error Correction Codes (ECCs) are …

Neutron irradiation testing and analysis of a fault-tolerant risc-v system-on-chip

DA Santos, AMP Mattos, LM Luza… - … on Defect and Fault …, 2022 - ieeexplore.ieee.org
The radiation in harsh environments affects electronic systems, inducing permanent and
temporary errors. These effects lead to unpredictable behaviors detrimental to critical …

Multi-bit data flow error detection method based on SDC vulnerability analysis

Z Yan, Y Zhuang, W Zheng, J Gu - ACM Transactions on Embedded …, 2023 - dl.acm.org
One of the most difficult data flow errors to detect caused by single-event upsets in space
radiation is the Silent Data Corruption (SDC). To solve the problem of multi-bit upsets …

A machine learning-driven edac method for space-application memory

J Chen, M Andjelkovic, M Krstic… - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
Space-based applications are susceptible to the effects of energetic particles, resulting in
single-event effects (SEEs). This vulnerability becomes critical during a solar particle event …

Fault tolerant micro-programmed control unit for SEU and MBU mitigation in space based digital systems

S Deepanjali, NM Sk - Microelectronics Reliability, 2024 - Elsevier
Abstract The Micro-Programmed Control Unit (MPCU) offers an alternative to conventional
hardwired control circuits by employing a control store for transmitting control signals …

A Hybrid Technique based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM arrays

D Gil-Tomás, LJ Saiz-Adalid, J Gracia-Morán… - IEEE …, 2024 - ieeexplore.ieee.org
MBU is an increasing challenge in SRAM memory, due to the chip's large area of SRAM,
and supply power scaling applied to reduce static consumption. Powerful ECCs can cope …

An Efficient Fault-Tolerant Protection Method for L0 BTB

J Nian, Z Liang, H Liu, M Yang - IEEE Transactions on Circuits …, 2022 - ieeexplore.ieee.org
Branch prediction structures are increasingly used in space processors due to their crucial
role in improving processor performance. Due to radiation effects such as Single Event …

Check-bit Region Exploration in Two-Dimensional Error Correction Codes

D Freitas, D Mota, D Coelho, H Fontinele… - IEEE …, 2024 - ieeexplore.ieee.org
The diversity of nanosatellite applications is increasingly attracting the scientific community's
attention. The main component of these satellites is the OnBoard Computer (OBC), which is …

A Lightweight Method for Detecting and Correcting Errors in Low-Frequency Measurements for In-Orbit Demonstrators

In the pursuit of enhancing the technological maturity of innovative magnetic sensing
techniques, opportunities presented by in-orbit platforms (IOD/IOV experiments) provide a …