Specialized on-chip accelerators are widely used to improve the energy efficiency of
computing systems. Recent advances in memory technology have enabled near-data …

An important challenge in multicore processors is the maintenance of cache coherence in a
scalable manner. Directory-based protocols save bandwidth and achieve scalability by …

One of the key scalability challenges of on-chip coherence in a multicore chip is the
coherence directory, which provides information on sharing of cache blocks. Shadow tags …

Data movement between the memory system and computation units is one of the most
critical challenges in designing high performance and energy-efficient computing systems …

Cache-coherent shared memory is critical for programmability in many-core systems.
Several directory-based schemes have been proposed, but dynamic, non-uniform sharing …

This paper investigates the use of DRAM caches for multi-node systems. Current systems
architect the DRAM cache as Memory-Side Cache (MSC), restricting the DRAM cache to …

As more processing cores are integrated into one chip and feature size continues to shrink,
the average access latency for remote nodes using directory-based coherence protocol …

A directory structure is traditionally employed for tracking coherence information of the
privately cached blocks in a cache-coherent chip-multiprocessor (CMP). The eviction of a …

As technology continues to scale, the need for more sophisticated coherence management
is becoming a necessity. The likely solution to this problem is the use of coherence …

A method and directory system that recognizes and represents the subset of sharing
patterns present in an application is provided. As used herein, the term sharing pattern …