Low power memristor based 7T SRAM using MTCMOS technique
VS Baghel, S Akashe - 2015 Fifth International Conference on …, 2015 - ieeexplore.ieee.org
In recent years demand of low power devices is increasing and the reason behind this is
scaling of CMOS technology. Due to the scaling, size of the chip decreases and number of …
scaling of CMOS technology. Due to the scaling, size of the chip decreases and number of …
[PDF][PDF] Comparative study of different low power design techniques for reduction of leakage power in CMOS VLSI circuits
PS Aswale, SS Chopade - International Journal of Computer Applications, 2013 - Citeseer
Scaling of transistor features sizes has improves performance, increase transistor density
and reduces the power consumption. A chip's maximum power consumption depends on its …
and reduces the power consumption. A chip's maximum power consumption depends on its …
Analysis of ATPMOS configurations-based 4× 1 multiplexer with estimation of power and delay
In this article, two consecutive augmenting transistor P-channel metal oxide semiconductor
(ATPMOS) configurations are proposed. These two ATPMOS configurations (ST ATPMOS …
(ATPMOS) configurations are proposed. These two ATPMOS configurations (ST ATPMOS …
Analysis Of Low Power Techniques For VLSI Circuit
N CHOUDHARY, S SHARMA - International Journal for …, 2016 - jrps.shodhsagar.com
This paper, presents a concept of the power optimization theory approach, the estimation
techniques and Power consumption is very important issue in VLSI circuit in recent days and …
techniques and Power consumption is very important issue in VLSI circuit in recent days and …
Optimization of Leakage Current and Leakage Power on 4x4 Array with SVL Technique Employed 7T SRAM Cell in Nanometer Regime.
S Singh, S Akashe - Journal of Active & Passive Electronic …, 2016 - search.ebscohost.com
In this era, 2D scaling of various electronic appliances both the logic circuits as well as the
memory based devices is eventually reaching their fundamental limits because of …
memory based devices is eventually reaching their fundamental limits because of …
[PDF][PDF] A Review On Power Effective Memristor Based SRAM Using MTCMOS
MRS Wasankar, AE Bhande - Citeseer
In recent years demand of low power devices is increasing and the reason behind this is
scaling of CMOS technology. Due to the scaling, size of the chip decreases and number of …
scaling of CMOS technology. Due to the scaling, size of the chip decreases and number of …
Design of High Performance and Low Leakage Voltage Controlled Oscillator Using MTCMOS Technique.
MS Kushwah, S Akashe - Journal of Active & Passive …, 2015 - search.ebscohost.com
The continuously scale down of technology, leakage current is growing exponentially. Ultra
low power applications have acquired a lot of attention in recent years. Energy-efficient …
low power applications have acquired a lot of attention in recent years. Energy-efficient …
[PDF][PDF] Minimization of Power in 10T D-FF using Leakage Reduction Technique
AS Kushwah - AJEC, 2015 - Citeseer
D-flip flop is a sequential circuit to store a bit or information. In digital environment, circuit
design is a very important parameter to require into account for creating a compact and …
design is a very important parameter to require into account for creating a compact and …
Efficiency of ATM networks in transporting TCP/IP traffic
JG Bredeson, DA Pillai - Proceedings of 28th Southeastern …, 1996 - ieeexplore.ieee.org
Finds the efficiency of ATM networks in transporting TCP/IP traffic. Different kinds of
protocols and compression techniques are used for these calculations. RFC 1483 is used to …
protocols and compression techniques are used for these calculations. RFC 1483 is used to …
[引用][C] An innovative technique on Low Power Leakage Reduction in CMOS circuits using Sleep transistors
C Rajagopal, L Kirubakaran