AccelWattch: A power modeling framework for modern GPUs

V Kandiah, S Peverelle, M Khairy, J Pan… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
Graphics Processing Units (GPUs) are rapidly dominating the accelerator space, as
illustrated by their wide-spread adoption in the data analytics and machine learning markets …

An agile approach to building RISC-V microprocessors

Y Lee, A Waterman, H Cook, B Zimmer, B Keller… - ieee …, 2016 - ieeexplore.ieee.org
The final phase of CMOS technology scaling provides continued increases in already vast
transistor counts, but only minimal improvements in energy efficiency, thus requiring …

A RISC-V vector processor with simultaneous-switching switched-capacitor DC–DC converters in 28 nm FDSOI

B Zimmer, Y Lee, A Puggelli, J Kwak… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with
fully integrated simultaneous-switching switched-capacitor DC–DC (SC DC–DC) converters …

Digital 2-/3-phase switched-capacitor converter with ripple reduction and efficiency improvement

J Jiang, WH Ki, Y Lu - IEEE Journal of Solid-State Circuits, 2017 - ieeexplore.ieee.org
This paper presents a digitally controlled 2-/3-phase 6-ratio switched-capacitor (SC) dc-dc
converter with low output voltage ripple and high efficiency. To achieve wide input and …

A dual-core risc-v vector processor with on-chip fine-grain power management in 28-nm fd-soi

JC Wright, C Schmidt, B Keller… - … Transactions on Very …, 2020 - ieeexplore.ieee.org
This work demonstrates a dual-core RISC-V system-on-chip (SoC) with integrated fine-grain
power management. The 28-nm fully depleted silicon-on-insulator (FD-SOI) SoC integrates …

Strober: Fast and accurate sample-based energy simulation for arbitrary RTL

D Kim, A Izraelevitz, C Celio, H Kim, B Zimmer… - ACM SIGARCH …, 2016 - dl.acm.org
This paper presents a sample-based energy simulation methodology that enables fast and
accurate estimations of performance and average power for arbitrary RTL designs. Our …

[PDF][PDF] A multipurpose formal risc-v specification

T Bourgeat, I Clester, A Erbsen… - arXiv preprint arXiv …, 2021 - people.csail.mit.edu
RISC-V is a relatively new, open instruction set architecture with a mature ecosystem and an
official formal machinereadable specification. It is therefore a promising playground for …

A fully integrated battery-powered system-on-chip in 40-nm CMOS for closed-loop control of insect-scale pico-aerial vehicle

X Zhang, M Lok, T Tong, SK Lee… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
We demonstrate a fully integrated system-on-chip (SoC) optimized for insect-scale flapping-
wing pico-aerial vehicles. The SoC is able to meet the stringent weight, power, and real-time …

A 16-core voltage-stacked system with adaptive clocking and an integrated switched-capacitor dc–dc converter

SK Lee, T Tong, X Zhang, D Brooks… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
This paper presents a 16-core voltage-stacked system with adaptive frequency clocking
(AFClk) and a fully integrated voltage regulator that demonstrates efficient on-chip power …

Simpler, more efficient design

B Nikolić - ESSCIRC Conference 2015-41st European Solid …, 2015 - ieeexplore.ieee.org
Design of custom integrated circuits has become prohibitively expensive for many
application domains. As a result, these domains often choose to implement the desired …