FPGA Implementation of an ASIP for high throughput DFT/DCT 1D/2D engine
HM Hassan, AF Shalash… - 2011 IEEE International …, 2011 - ieeexplore.ieee.org
In this paper, A novel architecture of an Application Specific Instruction Processor (ASIP) for
scalable DFT/IDFT DCT/IDCT ID (N-point) and 2D (N× M point) engine is proposed. An in …
scalable DFT/IDFT DCT/IDCT ID (N-point) and 2D (N× M point) engine is proposed. An in …
Design architecture of generic DFT/DCT 1D and 2D engine controlled by SW instructions
HM Hassan, AF Shalash… - 2010 IEEE Asia Pacific …, 2010 - ieeexplore.ieee.org
In this paper, a hardware implementation for generic DFT/IDFT DCT/IDCT 1D (N-point) and
2D (N× M point) processor is proposed, as N/M in the form of 2 x× 3 y to support different …
2D (N× M point) processor is proposed, as N/M in the form of 2 x× 3 y to support different …