Microparallelism and high-performance protein matching

B Alpern, L Carter, K Su Gatlin - Proceedings of the 1995 ACM/IEEE …, 1995 - dl.acm.org
The Smith-Waterman algorithm is a computationally-intensive string-matching operation that
is fundamental to the analysis of proteins and genes. In this paper, we explore the use of …

Pydgin: generating fast instruction set simulators from simple architecture descriptions with meta-tracing JIT compilers

D Lockhart, B Ilbeyi, C Batten - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
Instruction set simulators (ISSs) remain an essential tool for the rapid exploration and
evaluation of instruction set extensions in both academia and industry. Due to their …

Accurately timed transaction level models for virtual prototyping at high abstraction level

K Lu, D Müller-Gritschneder… - … Design, Automation & …, 2012 - ieeexplore.ieee.org
Transaction level modeling (TLM) improves the simulation performance by raising the
abstraction level. In the TLM 2.0 standard based on OSCI SystemC, a single transaction can …

[PDF][PDF] 二进制翻译技术研究综述

谢汶兵, 田雪, 漆锋滨, 武成岗, 王俊, 罗巧玲 - 软件学报, 2024 - jos.org.cn
随着信息技术的快速发展, 涌现出各种新型处理器体系结构. 新的体系结构出现为处理器多样化
发展带来机遇的同时也提出了巨大挑战, 需要兼容运行已有软件, 确保较为丰富的软件生态群 …

Accelerate cycle-level full-system simulation of multi-core RISC-V systems with binary translation

X Guo, R Mullins - arXiv preprint arXiv:2005.11357, 2020 - arxiv.org
It has always been difficult to balance the accuracy and performance of ISSs. RTL simulators
or systems such as gem5 are used to execute programs in a cycle-accurate manner but are …

[PDF][PDF] Atomic Instruction Translation Towards A Multi-Threaded QEMU.

A Rigo, A Spyridakis, D Raho - ECMS, 2016 - scs-europe.net
In the context of system emulation, the sophistication of the emulator usually grows with the
complexity of the target system model. Particularly, emulating precisely a certain CPU …

DSP instruction set simulation

F Brandner, N Horspool, A Krall - Handbook of Signal Processing Systems, 2013 - Springer
An instruction set simulator is an important tool for system architects and for software
developers. However, when implementing a simulator, there are many choices which can be …

Co-optimizing hardware design and meta-tracing just-in-time compilation

B Ilbeyi - 2019 - search.proquest.com
Performance of computers has enjoyed consistent gains due to the availability of faster and
cheaper transistors, more complex hardware designs, and better hardware design tools …

Overview on Binary Translation Technology Research

谢汶兵, 田雪, 漆锋滨, 武成岗, 王俊, 罗巧玲 - Journal of Software, 2024 - jos.org.cn
随着信息技术的快速发展, 涌现出各种新型处理器体系结构. 新的体系结构出现为处理器多样化
发展带来机遇的同时也提出了巨大挑战, 需要兼容运行已有软件, 确保较为丰富的软件生态群 …

[PDF][PDF] Boosting instruction set simulator performance with parallel block optimisation and replacement

B Alexander, S Donnellan… - … of the Thirty …, 2012 - crpit.scem.westernsydney.edu.au
Time-to-market is a critical factor in the commercial success of new consumer devices. To
minimise delays, system developers and third party software vendors must be able to test …