A 28-nm 75-fsrms Analog Fractional- Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle …
W Wu, CW Yao, K Godbole, R Ni… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
An analog fractional-sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
W Wu, CW Yao, C Guo, PY Chiang… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-phase-locked
loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To …
loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To …
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking
This article presents a fractional-N frequency synthesizer architecture that is able to
overcome the limitations of conventional bang-bang phase-locked loops. A digital …
overcome the limitations of conventional bang-bang phase-locked loops. A digital …
A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter
This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
A 0.65-V 12–16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM
This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …
A 23-GHz low-phase-noise digital bang–bang PLL for fast triangular and sawtooth chirp modulation
D Cherniak, L Grimaldi, L Bertulessi… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
This paper describes a 23-GHz digital bang-bang phase-locked loop (PLL) fabricated in 65-
nm CMOS for millimeter-wave frequency-modulated continuous-wave radars. The presented …
nm CMOS for millimeter-wave frequency-modulated continuous-wave radars. The presented …
A D-band joint radar-communication CMOS transceiver
A-band joint radar-communication complementary metal–oxide–semiconductor (CMOS)
transceiver featuring a dual-function mode multiplexer, a power-combining PA with high …
transceiver featuring a dual-function mode multiplexer, a power-combining PA with high …
A Low-Noise Fractional- Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications
In this paper, we propose a 60-GHz fractional-digital frequency synthesizer aimed at
reducing its phase noise (PN) at both the flicker () and thermal () regions while minimizing its …
reducing its phase noise (PN) at both the flicker () and thermal () regions while minimizing its …
Low-jitter frequency generation techniques for 5G communication: A tutorial
W Wu - IEEE Solid-State Circuits Magazine, 2021 - ieeexplore.ieee.org
5G is the latest global wireless standard, known as the fifth generation of cellular mobile
communication technology. Compared to 4G LTE, 5G increases peak data rates and …
communication technology. Compared to 4G LTE, 5G increases peak data rates and …
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration
In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-Nmultiplying delay-
locked loop (MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed …
locked loop (MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed …