A single-cycle tree-based 64-bit binary comparator with constant-delay (CD) logic realized in
a 65-nm, 1-V CMOS process is presented in this paper. Unlike dynamic logic yet domino …

A new small‐swing domino logic that reduces the signal amplitude by adding twist‐
connected PMOS and NMOS transistors in the conventional domino logic is presented. The …

Data processing performed by adder circuits need to achieve low delay and low power at
the same time while maintaining low cost, due to the steep growth in mobile computation …

Present paper analyses different aspects of “Low Power-High Speed”(LP-HS) logic in favour
of present day ULSI system focus. At first, the speed-power efficiency of LP-HS logic is …

The incessant growth of devices such as mobile phones, digital cameras, and other portable
electronic gadgets has led to a higher amount of research being dedicated to the low power …

In VLSI, major power consumption is due to dynamic switching power and leakage power.
Dynamic logic is used to reduce the switching power using pre charge technique, in that …

Abstract Parallel Prefix Radix 2 8 bit Comparators using Constant Delay (CD) logic is
presented in this paper. The constant delay logic pre discharges the output to zero logic and …

A 148ps, single-cycle 64-bit Ling adder with Constant-Delay (CD) logic implemented in the
critical path is fabricated in a 65nm, 1V CMOS process. The pre-evaluation and constant …

An adiabatic constant delay (ACD) logic style is proposed in this paper, for full-custom high-
speed and low power applications. The characteristic of ACD logic style will not depend …

In this article, novel leakage control techniques are adopted in Feed-Through Logic (FTL) for
low power high-speed designs. The FTL design has a unique feature; the outputs are …