A semiconductor memory device of an embodiment includes a substrate, a first conductive
layer provided above the substrate, the first conductive layer being spaced apart from the …

A nonvolatile memory device includes a memory cell array and a row decoder. The memory
cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of …

A nonvolatile memory device includes a memory cell array, a voltage generator, a page
buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality …

The disclosure provides a circuit structure for storage and retrieval of data, and related
methods. The circuit structure may include drive transistor having a source terminal, a drain …

(57) ABSTRACT A nonvolatile memory device includes a memory cell array, a voltage
generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array …

A nonvolatile memory device includes a memory cell array and a row decoder. The memory
cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of …

A storage unit includes a latch, and the latch provides a first storage bit. The storage unit
further includes a first MOS transistor. A gate of the first MOS transistor is connected to the …

A nonvolatile memory device includes a memory cell array and a row decoder. The memory
cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of …

The disclosed technology relates to a non-volatile (NV) static random-access memory
(SRAM) device, and to a method of operating the same. The NV-SRAM device includes a …

A semiconductor memory device includes a first transistor connected between a high
voltage line connected to a first end of a memory element and a first power supply terminal …