Combined DVFS and mapping exploration for lifetime and soft-error susceptibility improvement in MPSoCs
Energy and reliability optimization are two of the most critical objectives for the synthesis of
multiprocessor systems-on-chip (MPSoCs). Task mapping has shown significant promise as …
multiprocessor systems-on-chip (MPSoCs). Task mapping has shown significant promise as …
The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic
The paradigm of logical computation on stochastic bit streams has several key advantages
compared to deterministic computation based on binary radix, including error-tolerance and …
compared to deterministic computation based on binary radix, including error-tolerance and …
Memory-aware task scheduling with communication overhead minimization for streaming applications on bus-based multiprocessor system-on-chips
Inter-core communication introduces overheads in task schedules on Multiprocessor System-
on-Chips (MPSoCs). Inter-core communication overhead not only negatively impacts the …
on-Chips (MPSoCs). Inter-core communication overhead not only negatively impacts the …
Quasi-static fault-tolerant scheduling schemes for energy-efficient hard real-time systems
This paper investigates fault tolerance and dynamic voltage scaling (DVS) in hard real-time
systems. The authors present quasi-static task scheduling algorithms that consist of offline …
systems. The authors present quasi-static task scheduling algorithms that consist of offline …
Distributed sensor network-on-chip for performance optimization of soft-error-tolerant multiprocessor system-on-chip
As transistor density continues to increase with the advent of nanotechnology, reliability
issues raised by more frequently appeared soft errors are becoming even more critical to the …
issues raised by more frequently appeared soft errors are becoming even more critical to the …