Balancing system level pipelines with stage voltage scaling

H Guo, S Parameswaran - … on VLSI: New Frontiers in VLSI …, 2005 - ieeexplore.ieee.org
This paper presents an approach to dynamically balance the pipeline by scaling the stage
supply voltages. Simulation results show that by such an approach about 50% improvement …

Optimisation of the execution time inspired in Cross Layer design using effective load balancing in a LAN-WLAN environment

EM Macias, D Sanchez, A Suarez… - International Journal …, 2009 - inderscienceonline.com
A combination of wireless and wired network can be used to improve the execution time of
non-scientific applications at a very reduced cost. In previous works we have presented …

[PDF][PDF] Hardware-software co-design for reconfigurable field programmable gate arrays using mixed-integer programming

FM Ali, H Al-Hamadi, A Ghoniem, HD Sherali - Informatica, 2012 - informatica.si
This paper presents a novel mixed-integer programming formulation for scheduling non-
preemptive, aperiodic, hard real-time tasks with precedence constraints. It provides an …

A library for load balancing in master/slave applications on a LAN-WLAN environment

D Sanchez, EM Macias, A Suárez - 12th Euromicro Conference …, 2004 - ieeexplore.ieee.org
A combination of a local area network (LAN) and a wireless LAN (WLAN) is a useful
environment for doing parallel computing. We use this infrastructure to implement …

An embedded object approach to embedded system development

T Vallius - 2009 - oulurepo.oulu.fi
Building an embedded system from an idea to a product is a slow and expensive process
requiring a lot of expertise. Depending on the developer's expertise, the required quantity …

A Library for Load Balancing in Master/Slave Applications on a LAN-WLAN Environment

S David - 12th Euromicro Conference on Parallel, Distributed …, 2004 - computer.org
A combination of a Local Area Network (LAN) and a Wireless LAN (WLAN) is a useful
environment for doing parallel computing. We use this infrastructure to implement …

Hardware/Software partitioning based on Simulated Annealing

DC Sánchez Rodríguez, J Catellano… - 2000 - accedacris.ulpgc.es
A software implementation often can not satisfy embedded systems timing constraints. This
problem can be solved by adding specifíc hardware to the system. Lately, it has been …

Efficient image processing in resource-constrained visual sensor networks

H Du - 2006 - trace.tennessee.edu
Visual sensor networks (VSNs) that employ content-rich 2-D images or image sequences as
the basic media have been evolving rapidly in recent years. Besides the critical resource …

[引用][C] A design framework and genetic algorithm for digital design optimisation on FPGAs

MJW Savage - 2009 - ResearchSpace@ Auckland

[引用][C] Hardware/Software Partitioning based on Simulated Annealing

D Sánchez, JP Castellano, A Suárez - Modeling and Simulation, 2000