Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning accelerators
Techniques and configurations enhancing the performance of hardware (HW) accelerators
are provided. A schedule-aware, dynamically reconfigurable, tree-based partial sum …
are provided. A schedule-aware, dynamically reconfigurable, tree-based partial sum …
Method and apparatus with deep learning operations
H Kwon, HY Kim, P Hanmin… - US Patent App. 17 …, 2022 - Google Patents
An apparatus with deep learning includes: a systolic adder tree including adder trees
connected in row and column directions; and an input multiplexer connected to an input …
connected in row and column directions; and an input multiplexer connected to an input …
Programmable network segmentation for multi-tenant fpgas in cloud infrastructures
A Enrici, B Uscumlic - US Patent App. 17/221,057, 2022 - Google Patents
A network device for managing network segmentation in a network infrastructure includes at
least one processor, and at least one memory including computer program code, the at least …
least one processor, and at least one memory including computer program code, the at least …
Method for candidate selection and accelerator for performing candidate selection
TJ Ham, KIM Seonghak, J Sungjun… - US Patent …, 2023 - Google Patents
US11636173B2 - Method for candidate selection and accelerator for performing candidate
selection - Google Patents US11636173B2 - Method for candidate selection and …
selection - Google Patents US11636173B2 - Method for candidate selection and …