Fundamentally understanding and solving rowhammer
We provide an overview of recent developments and future directions in the RowHammer
vulnerability that plagues modern DRAM (Dynamic Random Memory Access) chips, which …
vulnerability that plagues modern DRAM (Dynamic Random Memory Access) chips, which …
DRAM bender: An extensible and versatile FPGA-based infrastructure to easily test state-of-the-art DRAM chips
To understand and improve DRAM performance, reliability, security, and energy efficiency,
prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art …
prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art …
CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost
DRAM chips are increasingly more vulnerable to read-disturbance phenomena (eg,
RowHammer and RowPress), where repeatedly accessing DRAM rows causes bitflips in …
RowHammer and RowPress), where repeatedly accessing DRAM rows causes bitflips in …
Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
Read disturbance in modern DRAM chips is a widespread phenomenon and is reliably used
for breaking memory isolation, a fundamental building block for building robust systems …
for breaking memory isolation, a fundamental building block for building robust systems …
{ABACuS}:{All-Bank} Activation Counters for Scalable and Low Overhead {RowHammer} Mitigation
We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation
technique that performance-, energy-, and area-efficiently scales with worsening …
technique that performance-, energy-, and area-efficiently scales with worsening …
[PDF][PDF] Abacus: All-bank activation counters for scalable and low overhead rowhammer mitigation
We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation
technique that performance-, energy-, and area-efficiently scales with worsening …
technique that performance-, energy-, and area-efficiently scales with worsening …
Cryptographically Enforced Memory Safety
M Unterguggenberger, D Schrammel… - Proceedings of the …, 2023 - dl.acm.org
C/C++ memory safety issues, such as out-of-bounds errors, are still prevalent in today's
applications. The presence of a single exploitable software bug allows an adversary to gain …
applications. The presence of a single exploitable software bug allows an adversary to gain …
How to Kill the Second Bird with One ECC: The Pursuit of Row Hammer Resilient DRAM
Error-correcting code (ECC) has been widely used in DRAM-based memory systems to
address the exacerbating random errors following the fabrication process scaling. However …
address the exacerbating random errors following the fabrication process scaling. However …
Revisiting row hammer: A deep dive into understanding and resolving the issue
H Wang, X Peng, Z Liu, X Huang, T Li, B Yang… - Microelectronics …, 2024 - Elsevier
Row hammer is a vulnerability in Dynamic Random Access Memory (DRAM) chips, whereby
repeatedly accessing a specific row in the DRAM chip may cause bit flips in memory cells …
repeatedly accessing a specific row in the DRAM chip may cause bit flips in memory cells …
Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips
A Olgun, M Osseiran, AG Yağlıkçı… - 2024 54th Annual …, 2024 - ieeexplore.ieee.org
We experimentally demonstrate the effects of read disturbance (RowHammer and
RowPress) and uncover the inner workings of undocumented read disturbance defense …
RowPress) and uncover the inner workings of undocumented read disturbance defense …