Low leakage zero ground bounce noise nanoscale full adder using source biasing technique
In this paper, three techniques of source biasing is presented for reduction in leakage power
at nano scale VLSI design. First technique of source biasing used NMOS sleep transistor at …
at nano scale VLSI design. First technique of source biasing used NMOS sleep transistor at …
Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI
In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for
low voltage logic design in state-of-the-art 28 nm ultra-thin body and box (UTBB) fully …
low voltage logic design in state-of-the-art 28 nm ultra-thin body and box (UTBB) fully …
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology
Recently, we proposed a low-granularity back-bias control technique [1] optimized for the
ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The …
ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The …
Ultra‐Low‐Voltage Self‐Body Biasing Scheme and Its Application to Basic Arithmetic Circuits
The gate level body biasing (GLBB) is assessed in the context of ultra‐low‐voltage logic
designs. To this purpose, a GLBB mirror full adder is implemented by using a commercial 45 …
designs. To this purpose, a GLBB mirror full adder is implemented by using a commercial 45 …
Comparison of ultra low power full adder cells in 22 nm fdsoi technology
SH Zadeh, T Ytterdal, S Aunet - 2018 IEEE Nordic Circuits and …, 2018 - ieeexplore.ieee.org
Five ultra low voltage and low power full adders have been designed and analyzed with
CMOS logic structure. To compare these adders, different metrics including worst case …
CMOS logic structure. To compare these adders, different metrics including worst case …
Effects of back-gate bias on the mobility and reliability of junction-less FDSOI transistors for 3-D sequential integration
Low thermal budget junction-less transistors with back-gate are fabricated as top-tier
devices for 3-D sequential integration. The impact of back-gate bias on carrier mobility and …
devices for 3-D sequential integration. The impact of back-gate bias on carrier mobility and …
Design of High-speed Power efficient full adder with Body-biasing
A Kumar, P Srivastava… - 2015 Global Conference …, 2015 - ieeexplore.ieee.org
A new 1-bit full adder cell has been introduced in this paper. According to this approach
body-biasing and semi domino logic both are used in a single full adder. Body-biasing …
body-biasing and semi domino logic both are used in a single full adder. Body-biasing …
An MTCMOS subthreshold-leakage reduction algorithm
SM Sharroush - 2020 2nd Novel Intelligent and Leading …, 2020 - ieeexplore.ieee.org
CMOS circuits that contain multiple branches in the pull-down network (PDN) suffer from the
trade-off between the leakage-power reduction and the improvement of the propagation …
trade-off between the leakage-power reduction and the improvement of the propagation …
[PDF][PDF] Digital-Based Analog Processing in Nanoscale CMOS ICs for IoT Applications
PF LEITE CORREIA DE TOLEDO - 2022 - tesidottorato.depositolegale.it
Abstract The Internet-of-Things (IoT) concept has been opening up a variety of applications,
such as urban and environmental monitoring, smart health, surveillance, and home …
such as urban and environmental monitoring, smart health, surveillance, and home …
Design of ultralow voltage-hybrid full adder circuit using GLBB scheme for energy-efficient arithmetic applications
K Sanapala, LR Shree, R Sakthivel - … Telecommunications: Proceedings of …, 2018 - Springer
In recent years, ultra low voltage (ULV) operation is gaining more importance to achieve
minimum energy consumption. In this paper, the performance of the gate level body biasing …
minimum energy consumption. In this paper, the performance of the gate level body biasing …