LVDS I/O interface for Gb/s-per-pin operation in 0.35-/spl mu/m CMOS
This paper presents the design and the implementation of input/output (I/O) interface circuits
for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) …
for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) …
A 0.14 pJ/b inductive-coupling inter-chip data transceiver with digitally-controlled precise pulse shaping
A transceiver for inductive-coupling is realized. By using a pulse-shaping circuit, the
transmitter energy is 0.11 pj/b. Due to device scaling from 180nm CMOS to 90nm CMOS, the …
transmitter energy is 0.11 pj/b. Due to device scaling from 180nm CMOS to 90nm CMOS, the …
A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link
A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock
rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a …
rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a …
A 1 Tb/s 3 W inductive-coupling transceiver for 3D-stacked inter-chip clock and data link
A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock
rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with …
rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with …
A 0.14 pJ/b inductive-coupling transceiver with digitally-controlled precise pulse shaping
A transceiver for inductive-coupling is realized. By using a pulse-shaping circuit, the
transmitter energy is 0.11 pJ/b. Due to device scaling from 180 nm CMOS to 90 nm CMOS …
transmitter energy is 0.11 pJ/b. Due to device scaling from 180 nm CMOS to 90 nm CMOS …
Scalable shared-buffering ATM switch with a versatile searchable queue
H Yamanaka, H Saito, H Kondoh… - IEEE Journal on …, 1997 - ieeexplore.ieee.org
The shared-buffering architecture is promising to make a large-scale ATM switch with small
buffer size. However, there are two important problems, namely, memory-access speed and …
buffer size. However, there are two important problems, namely, memory-access speed and …
Driver circuit device
T Nagamatsu, T Kuroda - US Patent 5,959,472, 1999 - Google Patents
In the constant current drive type driver used for an LVDS (low voltage differential signal)
interface, the parasitic capacitance of the package pins is charged and discharged …
interface, the parasitic capacitance of the package pins is charged and discharged …
Low power LVDS circuit for serial data communications
HC Chow, WW Sheen - 2005 International Symposium on …, 2005 - ieeexplore.ieee.org
With the advanced process, the supply voltage is decreased and power consumption is
reduced dramatically. However, the power supply of LVDS receiver side is constrained …
reduced dramatically. However, the power supply of LVDS receiver side is constrained …
QLWFQ: A queue length based weighted fair queueing algorithm in ATM networks
Y Ohba - Proceedings of INFOCOM'97, 1997 - ieeexplore.ieee.org
A work conserving O (1) per-VC queueing algorithm named QLWFQ (Queue Length based
Weighted Fair Queueing) for high-speed ATM networks is proposed. The basic process in …
Weighted Fair Queueing) for high-speed ATM networks is proposed. The basic process in …
A general purpose cell sequencer/scheduler for ATM switches
MR Hashemi, A Leon-Garcia - Proceedings of INFOCOM'97, 1997 - ieeexplore.ieee.org
Groups of cells, such as cells belonging to different priority levels, that are all placed in one
queue, can be identified by using labels or tags to distinguish them from each other. We …
queue, can be identified by using labels or tags to distinguish them from each other. We …