A survey of recent prefetching techniques for processor caches
S Mittal - ACM Computing Surveys (CSUR), 2016 - dl.acm.org
As the trends of process scaling make memory systems an even more crucial bottleneck, the
importance of latency hiding techniques such as prefetching grows further. However, naively …
importance of latency hiding techniques such as prefetching grows further. However, naively …
Learning memory access patterns
The explosion in workload complexity and the recent slow-down in Moore's law scaling call
for new approaches towards efficient computing. Researchers are now beginning to use …
for new approaches towards efficient computing. Researchers are now beginning to use …
High performance cache replacement using re-reference interval prediction (RRIP)
A Jaleel, KB Theobald, SC Steely Jr… - ACM SIGARCH computer …, 2010 - dl.acm.org
Practical cache replacement policies attempt to emulate optimal replacement by predicting
the re-reference interval of a cache block. The commonly used LRU replacement policy …
the re-reference interval of a cache block. The commonly used LRU replacement policy …
[图书][B] Memory systems: cache, DRAM, disk
B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stopping your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
Adaptive insertion policies for high performance caching
MK Qureshi, A Jaleel, YN Patt, SC Steely… - ACM SIGARCH …, 2007 - dl.acm.org
The commonly used LRU replacement policy is susceptible to thrashing for memory-
intensive workloads that have a working set greater than the available cache size. For such …
intensive workloads that have a working set greater than the available cache size. For such …
[图书][B] Architecture design for soft errors
S Mukherjee - 2011 - books.google.com
Architecture Design for Soft Errors provides a comprehensive description of the architectural
techniques to tackle the soft error problem. It covers the new methodologies for quantitative …
techniques to tackle the soft error problem. It covers the new methodologies for quantitative …
Data cache prefetching using a global history buffer
KJ Nesbit, JE Smith - 10th International Symposium on High …, 2004 - ieeexplore.ieee.org
A new structure for implementing data cache prefetching is proposed and analyzed via
simulation. The structure is based on a Global History Buffer that holds the most recent miss …
simulation. The structure is based on a Global History Buffer that holds the most recent miss …
SHiP: Signature-based hit predictor for high performance caching
The shared last-level caches in CMPs play an important role in improving application
performance and reducing off-chip memory bandwidth requirements. In order to use LLCs …
performance and reducing off-chip memory bandwidth requirements. In order to use LLCs …
Bounded geometries, fractals, and low-distortion embeddings
The doubling constant of a metric space (X, d) is the smallest value/spl lambda/such that
every ball in X can be covered by/spl lambda/balls of half the radius. The doubling …
every ball in X can be covered by/spl lambda/balls of half the radius. The doubling …
Die-stacked dram caches for servers: Hit ratio, latency, or bandwidth? have it all with footprint cache
Recent research advocates using large die-stacked DRAM caches to break the memory
bandwidth wall. Existing DRAM cache designs fall into one of two categories---block-based …
bandwidth wall. Existing DRAM cache designs fall into one of two categories---block-based …