Multistage linear feedback shift register counters with reduced decoding logic in 130-nm CMOS for large-scale array applications
Linear-feedback shift register (LFSR) counters have been shown to be well suited to
applications requiring large arrays of counters and can improve the area and performance …
applications requiring large arrays of counters and can improve the area and performance …
High-speed counter with novel LFSR state extension
This paper presents a high-speed counter architecture associated with novel LFSR state
extension. By employing the proposed state extension, an m-bit LFSR counter with states is …
extension. By employing the proposed state extension, an m-bit LFSR counter with states is …
Implementation of configurable linear feedback shift register in VHDL
S Mishra, RR Tripathi… - … Conference on Emerging …, 2016 - ieeexplore.ieee.org
This paper focus on the implementation of configurable linear feedback shift register
(CLFSR) in VHDL and evaluates its performance with respect to logic, speed and memory …
(CLFSR) in VHDL and evaluates its performance with respect to logic, speed and memory …
Design of multistage counters using linear feedback shift register
NB Nair, JP Anita - Inventive Communication and Computational …, 2022 - Springer
Applications such as single-photon detection require the use of large array of counters
within a small area. Linear feedback shift registers (LFSR) can be considered as the best …
within a small area. Linear feedback shift registers (LFSR) can be considered as the best …
[HTML][HTML] An infrastructure for accurate characterization of single-event transients in digital circuits
VS Veeravalli, T Polzer, U Schmid, A Steininger… - Microprocessors and …, 2013 - Elsevier
We present the architecture and a detailed pre-fabrication analysis of a digital measurement
ASIC facilitating long-term irradiation experiments of basic asynchronous circuits, which also …
ASIC facilitating long-term irradiation experiments of basic asynchronous circuits, which also …
Optimal stochastic computing randomization
CF Frasser, M Roca, JL Rossello - Electronics, 2021 - mdpi.com
Stochastic computing (SC) is a probabilistic-based processing methodology that has
emerged as an energy-efficient solution for implementing image processing and deep …
emerged as an energy-efficient solution for implementing image processing and deep …
Constant-time synchronous binary counter with minimal clock period
Y Hyun, IC Park - IEEE Transactions on Circuits and Systems II …, 2021 - ieeexplore.ieee.org
A synchronous binary counter is one of the basic components widely used in VLSI design,
and it is required to be fast and support a wide bit-width in many applications. However …
and it is required to be fast and support a wide bit-width in many applications. However …
New Programmable LFSR Counters with Automatic Encoding and State Extension
M Grymel - Electronics, 2024 - mdpi.com
An efficient method for detecting the end of a count of a linear feedback shift register (LFSR)
is presented. We show how this detector can be used to extend a maximum-length LFSR …
is presented. We show how this detector can be used to extend a maximum-length LFSR …
Federated machine learning architecture for searching malware
VI Hahanov, AS Saprykin - 2021 IEEE East-West Design & Test …, 2021 - ieeexplore.ieee.org
Modern technologies for searching viruses, cloud-edge computing, and also federated
algorithms and machine learning architectures are shown. The architectures for searching …
algorithms and machine learning architectures are shown. The architectures for searching …
Architecture and design analysis of a digital single-event transient/upset measurement chip
VS Veeravalli, T Polzer, A Steininger… - 2012 15th Euromicro …, 2012 - ieeexplore.ieee.org
This paper presents the architecture and a detailed design analysis of a digital
measurement chip which facilitates long-term irradiation experiments of basic asynchronous …
measurement chip which facilitates long-term irradiation experiments of basic asynchronous …