Computational memory cell and processing array device using memory cells
LL Shu, CH Chang, A Akerib - US Patent 10,521,229, 2019 - Google Patents
(57) ABSTRACT A memory cell that may be used for computation and processing array
using the memory cell are capable to performing a logic operation including a boolean AND …
using the memory cell are capable to performing a logic operation including a boolean AND …
Computational memory cell and processing array device using memory cells
LL Shu, CH Chang, A Akerib - US Patent 10,725,777, 2020 - Google Patents
A memory cell that may be used for computation and processing array using the memory cell
are capable to performing a logic operation including a boolean AND, a boolean OR, a …
are capable to performing a logic operation including a boolean AND, a boolean OR, a …
Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
LL Shu, E Ehrman - US Patent 10,998,040, 2021 - Google Patents
A memory cell and processing array that has a plurality of memory are capable of performing
logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic …
logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic …
Computational memory cell and processing array device using memory cells
LL Shu, CH Chang, A Akerib - US Patent 10,860,318, 2020 - Google Patents
A memory cell that may be used for computation and processing array using the memory cell
are capable to performing a logic operation including a boolean AND, a boolean OR, a …
are capable to performing a logic operation including a boolean AND, a boolean OR, a …
Systems and methods of phase-locked loop involving closed-loop, continuous frequency range, auto calibration and/or other features
YC Cheng - US Patent 9,729,159, 2017 - Google Patents
Abstract Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In
one illustrative implementation, a PLL circuit device may comprise voltage controlled …
one illustrative implementation, a PLL circuit device may comprise voltage controlled …
Systems and methods of phase-locked loop involving closed-loop, continuous frequency range, auto calibration and/or other features
YC Cheng - US Patent 9,722,618, 2017 - Google Patents
Abstract Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In
one illustrative implementation, a PLL circuit device may comprise voltage controlled …
one illustrative implementation, a PLL circuit device may comprise voltage controlled …
Systems and methods of phase-locked loop involving closed-loop, continuous frequency range, auto calibration and/or other features
YC Cheng - US Patent 9,608,651, 2017 - Google Patents
4,677.394 A 6, 1987 Vollmer 5,696,468 A 12, 1997 Nise 5,748,044 A 5, 1998 Xue 5,942,949
A 8, 1999 Wilson et al. 6,114,920 A 9, 2000 Moon et al. 6,175,282 B1 1/2001 Yasuda …
A 8, 1999 Wilson et al. 6,114,920 A 9, 2000 Moon et al. 6,175,282 B1 1/2001 Yasuda …
System and method for phase-locked loop (PLL) for high-speed memory interface (HSMI)
GC Tai - US Patent 7,659,783, 2010 - Google Patents
Phase-locked loops (PLLs) are an integral part of many electronics circuits and are
particularly important in commu nication circuits. For example, many digital systems use …
particularly important in commu nication circuits. For example, many digital systems use …
Systems and methods of phase-locked loop involving closed-loop, continuous frequency range, auto calibration and/or other features
YC Cheng - US Patent 9,083,356, 2015 - Google Patents
Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one
illustrative implementation, a PLL circuit device may comprise Voltage controlled oscilla tor …
illustrative implementation, a PLL circuit device may comprise Voltage controlled oscilla tor …