Unsupervised person image synthesis in arbitrary poses
We present a novel approach for synthesizing photo-realistic images of people in arbitrary
poses using generative adversarial learning. Given an input image of a person and a …
poses using generative adversarial learning. Given an input image of a person and a …
Improving test chip design efficiency via machine learning
Competitive position in the semiconductor field depends on yield which is becoming more
challenging to achieve high levels due to the increasing complexity associated with the …
challenging to achieve high levels due to the increasing complexity associated with the …
Back-end layout reflection for test chip design
Z Liu, RD Blanton - 2018 IEEE 36th International Conference on …, 2018 - ieeexplore.ieee.org
At advanced technology nodes, complex interactions between layout features and the
process can lead to manufacturability issues that reduce yield. Due to the huge number of …
process can lead to manufacturability issues that reduce yield. Due to the huge number of …
Efficient test chip design via smart computation
Submitted to the Special Issue on Machine Learning for CAD (ML-CAD). Competitive
strength in semiconductor field depends on yield. The challenges associated with designing …
strength in semiconductor field depends on yield. The challenges associated with designing …
[PDF][PDF] A Logic Test Chip for Optimal Test and Diagnosis.
B Niewenhuis - 2018 - kilthub.cmu.edu
The benefits of the continued progress in integrated circuit manufacturing have been
numerous, most notably in the explosion of computing power in devices ranging from cell …
numerous, most notably in the explosion of computing power in devices ranging from cell …
Logic Test Vehicles for High Resolution Diagnosis of Systematic FEOL/MEOL Yield Detractors
Y Lyu, L Yu, P Li, J Huang - 2023 IEEE International Test …, 2023 - ieeexplore.ieee.org
Test vehicles are important circuits for process yield learning at early stage. In-house
customized standard cell libraries should also be evaluated from the yield perspective. In …
customized standard cell libraries should also be evaluated from the yield perspective. In …
High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips
Z Liu, RDS Blanton - 2020 IEEE International Test Conference …, 2020 - ieeexplore.ieee.org
Test vehicles of various types that aim to identify yield detractors are essential for maturing a
new semiconductor process before high volume production. Due to large number of …
new semiconductor process before high volume production. Due to large number of …
Integrated Circuit Test Optimization for Comprehensive Defect Characterization
C Fang - 2021 - search.proquest.com
The relentless scaling of integrated circuits (IC) are bringing challenges to the manufacturing
process. The decreasing distance between transistors and complicated layout features …
process. The decreasing distance between transistors and complicated layout features …
A Test Chip Design for Automatic Insertion of Logic Circuit Demographics
Z Liu - 2020 - search.proquest.com
The continued scaling of integrated circuits (ICs) introduces complex interactions between
layout features, which can lead to manufacturability issues that reduce yield. In recent years …
layout features, which can lead to manufacturability issues that reduce yield. In recent years …
Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle
B Niewenhuis, B Ravikumar, Z Liu… - 2019 IEEE 37th VLSI …, 2019 - ieeexplore.ieee.org
Previous work on the Carnegie Mellon Logic Characterization Vehicle (CM-LCV) has
achieved optimal testability for static fault models. This work explores enhancements to the …
achieved optimal testability for static fault models. This work explores enhancements to the …