A comprehensive analysis of junctionless tri-gate (TG) FinFET towards low-power and high-frequency applications at 5-nm gate length

VB Sreenivasulu, V Narendar - Silicon, 2021 - Springer
Abstract Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate
lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless …

Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes

VB Sreenivasulu, V Narendar - AEU-International Journal of Electronics …, 2022 - Elsevier
Silicon (Si) ultrathin junctionless (JL) n-FinFET with LG= 3 nm and 1 nm are explored for the
first time by invoking Hf x Ti 1-x O 2 based high-k gate dielectric. The 3D device performance …

6Transistor SRAM cell designed using 18nm FinFET technology

RR Vallabhuni, P Shruthi, G Kavya… - 2020 3rd International …, 2020 - ieeexplore.ieee.org
The electronics devices are facing a foremost drawback of standby leakage, which will
severely impact the electronics industry from the past few decades. As well as the need for …

Analog and RF performance evaluation of junctionless accumulation mode (JAM) gate stack gate all around (GS-GAA) FinFET

B Kumar, R Chaujar - Silicon, 2021 - Springer
This work presents the analog and RF performance evaluation of Junctionless Accumulation
Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET, and the results acquired have …

Design and deep insights into sub-10 nm spacer engineered junctionless FinFET for nanoscale applications

N Vadthiya - ECS journal of solid state science and technology, 2021 - iopscience.iop.org
In this paper, we have studied the impact of various dielectric single-k (Sk) and dual-k (Dk)
spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric …

TCAD temperature analysis of gate stack gate all around (GS-GAA) FinFET for improved RF and wireless performance

B Kumar, R Chaujar - Silicon, 2021 - Springer
In this article, we investigated the impact of temperature variation on DC, analog, RF, and
wireless performance of Gate Stack Gate All Around (GS-GAA) FinFET using SILVACO Atlas …

Numerical study of JAM-GS-GAA FinFET: a Fin aspect ratio optimization for upgraded analog and intermodulation distortion performance

B Kumar, R Chaujar - Silicon, 2022 - Springer
This paper optimizes the fin aspect ratio (AR) of Junctionless Accumulation Mode Gate Stack
Gate All Around (JAM-GS-GAA) FinFET with constant conducting channel area for upgraded …

FinFET to GAA MBCFET: A Review and Insights

RR Das, TR Rajalekshmi, A James - IEEE Access, 2024 - ieeexplore.ieee.org
This review article presents a journey from Fin-shaped field effect transistor (FinFET) to gate-
all-around multi-bridge channel field effect transistor (GAA MBCFET) technology, unraveling …

Polarization induced doping and high-k passivation engineering on T-gate MOS-HEMT for improved RF/microwave performance

M Sharma, B Kumar, R Chaujar - Materials Science and Engineering: B, 2023 - Elsevier
High electron-mobility transistors (HEMTs) based on III-nitrides are well-known as ideal
choices for high-power, radio-frequency applications. HEMTs, on the other hand, must deal …

A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance

N Vadthiya, P Narware, V Bheemudu… - AEU-International Journal …, 2020 - Elsevier
FinFET for system-on-chip (SoC) applications like logic/SRAM need shorter fins, whereas in
analog/RF and global interconnect drivers need taller and multi-fins. To tackle this issue, we …