Power efficient low latency architecture for decoder: Breaking the ACS bottleneck
Viterbi decoder (VD) is the majority used decoder for convolutional codes which play a role
in WLAN and WSN applications. The trellis in VD needs proper analysis to calculate the …
in WLAN and WSN applications. The trellis in VD needs proper analysis to calculate the …
Carry Select Adder Using Square Root Techniques in Ripple Carry and BCD Adders
R Subramanyam, VAK Talluri… - 2024 IEEE 13th …, 2024 - ieeexplore.ieee.org
Carry select adder (CSA) finds application in increasing the speed of additions in various
processing units. However, the design of this CSA is a challenge because the gates used in …
processing units. However, the design of this CSA is a challenge because the gates used in …
Design of fault tolerant majority voter for error resilient TMR targeting micro to nano scale logic
M Goswami, S Chattopadhyay… - International Journal …, 2020 - inderscienceonline.com
The shrinking size of transistors for satisfying the increasing demand for higher density and
low power has made the VLSI circuits more vulnerable to faults. Therefore, new circuits in …
low power has made the VLSI circuits more vulnerable to faults. Therefore, new circuits in …
Double Balanced Mixer with noise reduction for RF Receiver using Cadence 180nm Technology
S Radha, G Krishna, KMS Sumanth… - 2020 6th …, 2020 - ieeexplore.ieee.org
RF receiver comprises of local oscillator, mixer and demodulator stages. Mixer circuit has its
own roles and responsibility in the receiver circuit. Single stage mixer faces problems like …
own roles and responsibility in the receiver circuit. Single stage mixer faces problems like …
Transformer Coupled Voltage Controlled Oscillator Using 180nm Technology in Cadence Tool
VCO finds role in a wide variety of applications. The frequency of the signal generated by
VCO depends on its input signal. Anti phase coupling is generally followed in VCOto obtain …
VCO depends on its input signal. Anti phase coupling is generally followed in VCOto obtain …
Design and FPGA Synthesis of an Efficient Synchronous Counter with Clock-Gating Techniques
SK Singh, MD Gupta, RK Chauhan - Nanoelectronics, Circuits and …, 2021 - Springer
In the proposed work, we focused on clock-gating-based synchronous counter. This paper
depicts the designing of high-speed synchronous counter with low dynamic power …
depicts the designing of high-speed synchronous counter with low dynamic power …
[PDF][PDF] Education Qualifications Name of the Degree Class
PGM Tech - Hands-On, 2020 - cbit.ac.in
6. Qualified in GATE 2019 (conducted by IIT, Madras) with score 415 validity 17 March 2019
to 16 March 2022. 7. Qualified in GATE 2015 (conducted by IIT, Kanpur) with score 413 …
to 16 March 2022. 7. Qualified in GATE 2015 (conducted by IIT, Kanpur) with score 413 …
Gabor Filter-Based Tonsillitis Analysis Using VHDL
Image analysis finds application in a wide variety of areas, namely tumour detection, security
purpose by monitoring the captured images, diagnosis of early-stage diseases in various …
purpose by monitoring the captured images, diagnosis of early-stage diseases in various …